Datasheet > MT12D436G-XX

MT12D436G-XX

更新时间： 2024-09-18 02:58:47

品牌	Logo	应用领域
镁光 - MICRON		动态存储器
页数	文件大小	规格书
17页	311K
描述
DRAM MODULE

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中文翻译

获取价格

数据手册

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MT12D436G-XX 数据手册

OBSOLETE

4, 8 MEG x 36

PARITY DRAM SIMMs

MT12D436

MT24D836

DRAM

MODULE

FEATURES

• JEDEC- and industry-standard pinout in a 72-pin,

single in-line memory module (SIMM)

• 16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity

versions

• High-performance CMOS silicon-gate process

• Single 5V ±10% power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

PIN ASSIGNMENT (Front View)

72-Pin SIMM

(DD-5) 4 Meg x 36 (shown)

(DD-6) 8 Meg x 36

(DD-7) 4 Meg x 36 Low Profile

• 2,048-cycle refresh distributed across 32ms

• FAST PAGE MODE (FPM) access cycle

• Multiple RAS# lines allow x18 or x36 widths

OPTIONS

• Timing

MARKING

60ns access

-6

• Packages

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

72-pin SIMM

72-pin SIMM (gold)

72-pin SIMM low profile (1.00")

Vss

DQ1

DQ19

DQ2

DQ20

DQ3

DQ21

DQ4

DQ22

Vcc

A10

DQ5

DQ23

DQ6

DQ24

DQ7

DQ25

DQ8

DQ26

NC (A11)

Vcc

DQ18

DQ36

Vss

CAS0#

CAS2#

CAS3#

CAS1#

RAS0#

DQ13

DQ31

DQ14

DQ32

Vcc

DQ33

DQ15

DQ34

DQ16

DQ35

DQ17

PRD1

PRD2

PRD3

PRD4

72-pin SIMM (gold) low profile (1.00")

KEY TIMING PARAMETERS

45 NC/RAS1#* 63

SPEED

110ns

RAC

60ns

35ns

30ns

CAC

15ns

WE#

DQ10

DQ28

DQ11

DQ29

DQ12

DQ30

-6

40ns

PART NUMBERS

33 NC/RAS3#* 51

PART NUMBER

CONFIGURATION

4 Meg x 36

8 Meg x 36

PLATING

HEIGHT

1.190"

1.000"

1.190"

RAS2#

DQ27

DQ9

MT12D436G-xx

MT12D436M-xx

MT12D436DG-xx

MT12D436DM-xx

MT24D836G-xx

MT24D836M-xx

xx = speed

Gold

Tin/Lead

Gold

Vss

*32MB version only

Tin/Lead

Gold

NOTE: Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

Tin/Lead

GENERAL DESCRIPTION

The MT12D436 and MT24D836 are randomly accessed

16MB and 32MB solid-state memories organized in a x36

configuration. During READ or WRITE cycles, each bit is

uniquely addressed through the 22 address bits, which are

entered 11 bits (A0-A10) at a time. RAS# is used to latch the

first 11 bits and CAS# the latter 11 bits. A READ or WRITE

cycle is selected with the WE# input. A logic HIGH on WE#

dictates READ mode, while a logic LOW on WE# dictates

WRITE mode. During a WRITE cycle, data-in (D) is latched

by the falling edge of CAS#. Since WE# goes LOW prior to

CAS# going LOW, the output pin(s) remain open (High-Z)

until the next CAS# cycle.

4, 8 Meg x 36 Parity DRAM SIMMs

DM45.pm5 – Rev. 3/97

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1997, Micron Technology, Inc.

12 3 4 5 6 7...17

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