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MSM9552 PDF预览

MSM9552

更新时间: 2024-09-25 10:45:15
品牌 Logo 应用领域
冲电气 - OKI 消费电路商用集成电路
页数 文件大小 规格书
7页 60K
描述
LSI for FM Multiplex Data Demodulation

MSM9552 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:QFP,针数:44
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PQFP-G44
长度:10.5 mm功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:RECTANGULAR
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.25 mm最大压摆率:32 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:9.5 mm
Base Number Matches:1

MSM9552 数据手册

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¡ Semiconductor  
MSM9552/MSM9553  
LSI for FM Multiplex Data Demodulation  
GENERAL DESCRIPTION  
The MSM9552 and MSM9553 are LSI devices which demodulate FM character multiplex signals in  
the DARC (DAta Radio Channel)* format to acquire digital data. The MSM9552 and MSM9553  
operate on 5V and 3V, respectively. In the DARC format, baseband signals at ordinary FM  
broadcasting frequencies are multiplexed with 16k-bps digital data which are L-MSK-modulated at  
76kHz.  
Each of the MSM9552 and MSM9553 has a bandpass filter consisting of SCF, frame synchroniza-  
tion circuit, error correction circuit, etc. on a single chip.  
So, a system for acquisition of digital data can be easily constructed by externally mounting an FM  
receiver tuner, microcontroller for control, and memory for temporary storage of data.  
The MSM9552 and MSM9553 have a simple configuration, and are equipped with only necessary  
functions. By making changes to software for the external microcontroller, the MSM9552 and  
MSM9553 can meet the various requirements of FM multiplex broadcasting services which will be  
offered in future.  
TheseLSIdevicesarebestsuitedtotheradiosetsandinformationdevicesforFMcharactermultiplex  
broadcasting, which started in Japan in October 1994. Especially, the MSM9553 is suitable for  
portable units.  
* DARC is a registered trademark of NHK ENGINEERING SERVICES, INC.  
Note that a contract needs to be made with NHK Engineering Service if a manufacturer produces/  
sells electronic equipment utilizing the DARC technology.  
FEATURES  
• Built-in bandpass filter (SCF)  
• Built-in block synchronization circuit and frame synchronization circuit  
• Setting of the number of synchronization protecting stages  
• Regeneration of data clocks by digital PLL  
• 1T delay detection  
• Built-in error correction circuit  
• Built-in layer 4 and layer 2 CRC check circuit  
• Microcontroller parallel interface  
• Clock output for external devices (64kHz to 8.192MHz selectable)  
• International standard frame format  
• Power source:  
• Package  
5V (MSM9552), 3V (MSM9553)  
44-pin plastic QFP (QFP44-P-910-0.80-2K)  
1

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