512K x 8 SRAM
MSM8512 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : January 1999
524,288 x 8 CMOS Static RAM
Description
Features
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70nsto100nsavailable.Thedeviceisavailablein
three 32 pin ceramic packages, one being the
space saving VILTM. The device has a low power
standby version which supports data retention
mode and is directly TTL compatible.
Fast Access Times of 70/85/100 ns
JEDEC standard package.
Average Operating Power 385 mW (max)
Standby Power
550 µW (max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
All versions can be screened in accordance with
MIL-STD-883C.
May be processed in accordance with MIL-STD-883C
Block Diagram
Pin Definition
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A18
A16
A14
A12
A7
Vcc
A15
A17
WE
A13
A8
A18
A17
2
3
A16
A15
A14
A13
A12
A11
A10
A9
4,194,304
BIT
4
5
6
A6
A5
A4
MEMORY
ARRAY
S,V
Package
Top View
7
A9
8
A11
OE
A10
CS
D7
9
A3
A2
A1
10
11
12
13
14
15
16
A0
D0
D6
D5
D0
D7
D1
D2
GND
COLUMN I/O
I/O
BUFFER
D4
D3
COLUMN DECODE
Y ADDRESS BUFFER
WE
D1
D2
4
A12
A14
A16
A18
VCC
A15
CS2
14
15
16
17
18
19
20
OE
CS
3
2
TOP VIEW
J
GND
D3
1
D4
32
31
30
D5
D6
Pin Functions
Package Details
A0-A18
D0-7
CS
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
Power (+5V)
Ground
Pin Count
Descripion
Package Type
32
32
32
0.6" Dual-in-Line (DIP)
0.1" Vertical-in-line (VILTM)
Extended JLCC Package
S
V
J
OE
WE
VCC
GND