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MSM832JI-020 PDF预览

MSM832JI-020

更新时间: 2024-11-30 04:50:31
品牌 Logo 应用领域
MOSAIC 静态存储器内存集成电路
页数 文件大小 规格书
11页 132K
描述
Standard SRAM, 32KX8, 20ns, CMOS, CQCC32, JLCC-32

MSM832JI-020 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.11
最长访问时间:20 nsJESD-30 代码:R-CQCC-J32
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:32
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子位置:QUAD
Base Number Matches:1

MSM832JI-020 数据手册

 浏览型号MSM832JI-020的Datasheet PDF文件第2页浏览型号MSM832JI-020的Datasheet PDF文件第3页浏览型号MSM832JI-020的Datasheet PDF文件第4页浏览型号MSM832JI-020的Datasheet PDF文件第5页浏览型号MSM832JI-020的Datasheet PDF文件第6页浏览型号MSM832JI-020的Datasheet PDF文件第7页 
32K x 8 SRAM  
MSM832 - 020/025/35  
11403 West Bernado Court, Suite 100, San Diego, CA 92127.  
Tel No: (619) 674 2233, Fax No: (619) 674 2230  
Issue 4.3 : Nov 1998  
32,768 x 8 CMOS High Speed Static RAM  
Description  
Features  
The MSM832 is a high speed Static RAM organ-  
ised as 32K x 8 available with access times of 20  
25 or 35 ns. The device is available in four ce-  
ramic package options including the high denisty  
VIL™ package. It features completely static  
operation with a low power standby mode and is  
3.0V battery back-up compatible. It is directly TTL  
compatible and has common data inputs and  
outputs.  
• Fast Access Times of 20/25/35 ns.  
• JEDECStandardfootprint.  
• Operating Power 908 mW (max)  
• Low Power Standby 11 mW (max) -L version.  
• LowVoltageDataRetention.  
• DirectlyTTLcompatible.  
The device may be screened in accordance with  
MIL-STD-883.  
• Completely Static Operation.  
Block Diagram  
Pin Definitions  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0 10  
D0 11  
D1 12  
D2 13  
GND 14  
1
2
3
4
5
6
7
8
9
28  
V
CC  
27 WE  
26 A13  
25 A8  
24 A9  
23 A11  
22 OE  
21 A10  
20 CS  
19 D7  
18 D6  
17 D5  
16 D4  
15 D3  
A3  
A4  
A5  
A6  
A7  
A8  
A12  
A13  
A14  
X
Row  
Memory Array  
Address  
Decoder  
Buffer  
V,T  
PACKAGE  
TOP VIEW  
512 X 512  
D0  
D7  
Column I/O  
I/O  
Buffer  
Column Decoder  
Y Address Buffer  
WE  
OE  
CS  
29 A8  
28 A9  
27 A11  
26 NC  
25 OE  
24 A10  
23 CS  
22 D7  
21 D6  
A6  
A5  
A4  
A3  
A2  
5
6
7
8
9
J,W  
PACKAGE  
TOP VIEW  
A1 10  
A0 11  
NC 12  
D0 13  
Package Details  
PinFunctions  
Pin Count  
Description  
Package Type  
A0-A14  
D0-7  
CS  
Address inputs  
DataInput/Output  
32  
28  
28  
32  
J-LeadedChipCarrier(JLCC)  
0.1"Vertical-in-LIne(VILTM)  
0.3"Dual-in-line(SKINNYDIP)  
LeadlessChipCarrier(LCC)  
J
V
T
Chip Select  
OutputEnable  
Write Enable  
Power(+5V)  
Ground  
OE  
WE  
W
VCC  
GND  
1

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