Datasheet > MSM51V8221A-40GS-K

MSM51V8221A-40GS-K

更新时间： 2024-11-27 04:47:15

品牌	Logo	应用领域
冲电气 - OKI		光电二极管
页数	文件大小	规格书
17页	200K
描述
Memory Circuit, 256KX8, CMOS, PDSO28, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-28

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E2L0054-28-Z2

This version: Dec. 1998

Previous version: Mar. 1998

¡ Semiconductor

MSM51V8221A

¡ Semiconductor

MSM51V8221A

262,214-Word ¥ 8-Bit Field Memory

DESCRIPTION

TheOKIMSM51V8221Aisahighperformance2-Mbit, 256K¥8-bit, FieldMemory. Itisdesigned

for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital

movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity

TVs and VTRs, exclusively. The MSM51V8221A is not designed for the other use or high end

use in medical systems, professional graphics systems which require long term picture, and

data storage systems and others. The 2-Mbit capacity fits one field of a conventional NTSC TV

screen.

Each of the 8-bit planes has separate serial write and read ports. These employ independent control

clockstosupportasynchronousreadandwriteoperations. Differentclockratesarealsosupported,

which allow alternate data rates between write and read data streams.

The MSM51V8221A provides high speed FIFO, First-In First-Out, operation without external

refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial

access operation, so that serial read and/or write control clock can be halted high or low for any

duration as long as the power is on. Internal conflicts of memory access and refreshing operations

are prevented by special arbitration logic.

TheMSM51V8221A'sfunctionissimple,andsimilartoadigitaldelaydevicewhosedelay-bit-length

is easily set by reset timing. The delay length, and the number of read delay clocks between write

and read, is determined by externally controlled write and read reset timings.

AdditionalSRAMserialregisters, orlinebuffersfortheinitialaccessof256¥8-bitenablehighspeed

first-bit-access with no clock delay just after the write or read reset timings.

The MSM51V8221A is similar in operation and functionality to OKI 1-Mbit Field Memory

MSM51V4221C. It has a write mask function or input enable function (IE), and read-data skipping

function or output enable function (OE). The differences between write enable (WE) and input

enable(IE),andbetweenreadenable(RE)andoutputenable(OE)arethatWEandREcanstopserial

write/readaddressincrements,butIEandOEcannotstoptheincrement,whenwrite/readclocking

is continuously applied to MSM51V8221A. The input enable (IE) function allows the user to write

intoselectedlocationsofthememoryonly,leavingtherestofthememorycontentsunchanged. This

facilitates data processing to display a "picture in picture" on a TV screen.

1/16

12 3 4 5 6 7...17

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与MSM51V8221A-40GS-K相关器件

型号	品牌	获取价格	描述	数据表
MSM51V8221A-40JS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-28
MSM51V8221A-40ZS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PZIP28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, ZIP-28
MSM51V8222A	OKI	获取价格	262,214-Word x 8-Bit Field Memory
MSM51V8222A-30GS-K	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PDSO28, 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-28
MSM51V8222A-30JS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-28
MSM51V8222A-30ZS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PZIP28, 0.400 INCH HEIGHT, 1.27 MM PITCH, PLASTIC, ZIP-28
MSM51V8222A-40JS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PDSO28, 0.400 INCH, 1.27 MM PITCH, PLASTIC, SOJ-28
MSM51V8222A-40ZS	OKI	获取价格	Memory Circuit, 256KX8, CMOS, PZIP28, 0.400 INCH HEIGHT, 1.27 MM PITCH, PLASTIC, ZIP-28
MSM51X17400F	OKI	获取价格	4,194,304-Word 】 4-Bit DYNAMIC RAM : FAST PAG
MSM51X17400F-10	OKI	获取价格	4,194,304-Word 】 4-Bit DYNAMIC RAM : FAST PAG

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