MSC8102
Rev. 12, 4/2005
Freescale Semiconductor
Technical Data
MSC8102
Quad Core 16-Bit Digital Signal Processor
The raw processing power of
this highly integrated system-
on-a-chip device enables
developers to create next-
generation networking
products that offer
SC140
SC140
SC140
SC140
Extended Core
Extended Core
Extended Core
Extended Core
MQBus
128
128
64
SQBus
Boot
tremendous channel
Local Bus
ROM
densities, while maintaining
system flexibility, scalability,
and upgradeability. The
MSC8102 is offered in two
core speed levels: 250 and
275 MHz.
IP Master
M2
32 Timers
RAM
Memory
RS-232
Controller*
UART
PLL/Clock
PLL
4 TDMs
GPIO
GIC
GPIO Pins
Interrupts
IPBus
32
JTAG Port
JTAG
What’s New?
Rev. 12 includes the following
changes:
8 Hardware
Semaphores
•
New Section 2.5.2 adds start-
Internal Local Bus
SIU
64
up sequence timing.
Direct
Slave
DSI Port
Interface
(DSI)
System
32/64
60x-compatible
System Bus
DMA
Bridge
Interface
Registers
64
Memory
Controller*
Internal System Bus
32/64
*There is a single memory controller that controls access to both the local bus and the system bus.
Figure 1. MSC8102 Block Diagram
The MSC8102 is a highly integrated system-on-a-chip that combines four StarCore™ SC140 extended cores with
an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose
timers, a flexible system interface unit (SIU), and a multi-channel DMA engine. The four extended cores can
deliver a total 4400 DSP MMACS performance at 275 MHz. Each core has four arithmetic logic units (ALUs),
internal memory, a write buffer, and two interrupt controllers. The MSC8102 targets high-bandwidth highly
computational DSP applications and is optimized for wireless transcoding and packet telephony as well as high-
bandwidth base station applications. The MSC8102 delivers enhanced performance while maintaining low power
dissipation and greatly reducing system cost.
© Freescale Semiconductor, Inc., 2002, 2005. All rights reserved.