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MSC8101M1250F PDF预览

MSC8101M1250F

更新时间： 2024-11-04 22:51:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
104页 1735K
描述
Network Digital Signal Processor

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中文翻译

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MSC8101M1250F 技术参数

生命周期：Transferred零件包装代码：BGA
包装说明：FBGA, BGA357,19X19,50针数：332
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.22
Is Samacsys：N地址总线宽度：32
桶式移位器：NO位大小：16
边界扫描：YES最大时钟频率：62.5 MHz
外部数据总线宽度：64格式：FIXED POINT
内部总线架构：SINGLEJESD-30 代码：S-PBGA-B332
长度：17 mm低功率模式：YES
端子数量：332封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA357,19X19,50
封装形状：SQUARE封装形式：GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.6,3.3 V
认证状态：Not QualifiedRAM（字数）：262144
座面最大高度：3.18 mm子类别：Digital Signal Processors
最大供电电压：1.7 V最小供电电压：1.5 V
标称供电电压：1.6 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：17 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

MSC8101M1250F 数据手册

 浏览型号MSC8101M1250F的Datasheet PDF文件第2页浏览型号MSC8101M1250F的Datasheet PDF文件第3页浏览型号MSC8101M1250F的Datasheet PDF文件第4页浏览型号MSC8101M1250F的Datasheet PDF文件第5页浏览型号MSC8101M1250F的Datasheet PDF文件第6页浏览型号MSC8101M1250F的Datasheet PDF文件第7页 
MSC8101  
Rev. 16, 11/2004  
Freescale Semiconductor  
Technical Data  
MSC8101  
Network Digital Signal Processor  
CPM  
SIU  
The Freescale MSC8101  
16-bit DSP is the first  
member of the family of  
DSPs based on the  
StarCore SC140 DSP core.  
The MSC8101 is available  
in three core speed levels:  
250, 275, and 300 MHz.  
64-bit System Bus  
Interrupt  
3 × FCC  
2 × MCC  
4 × SCC  
2 × SMC  
SPI  
MEMC  
PIT  
Controller  
UTOPIA  
Interface  
64/32-bit  
System  
Bus  
Timers  
Parallel I/O  
System Protection  
Reset Control  
Clock Control  
MII  
DMA  
Engine  
Baud Rate  
Generators  
•
•
•
SIC_EXT  
SIC  
Dual Ported  
RAM  
TDMs  
Interrupts  
{
Bridge  
2 × SDMA  
MEMC  
I2C  
RISC  
64-bit Local Bus  
128-bit QBus  
Other  
Peripherals  
Extended Core  
PIC  
Q2PPC  
Bridge  
Interrupts  
EFCOP  
Address  
Register  
File  
Data ALU  
Register  
File  
Program  
Sequencer  
Boot  
ROM  
8/16-bit  
Host  
HDI16  
Interface  
Address  
ALU  
Data  
ALU  
What’s New?  
Rev. 16 includes the following  
changes:  
SC140  
Core  
SRAM  
512 KB  
L1 Interface  
JTAG  
EOnCE™  
•
Changed most REFCLK  
references to DLLIN in  
Section 2.7.4.  
128-bit P-Bus  
64-bit XA Data Bus  
64-bit XB Data Bus  
Power  
Clock/PLL  
Management  
Figure 1. MSC8101 Block Diagram  
The Freescale MSC8101 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic  
logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very  
flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the  
MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32-  
bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet,  
and asynchronous transfer mode (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to  
multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data  
memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz  
clock with a 1.6 V core and independent 3.3 V input/output (I/O).  
© Freescale Semiconductor, Inc., 2001, 2004. All rights reserved.  
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