Datasheet > MS81V04160

MS81V04160

更新时间： 2024-09-25 22:23:51

品牌	Logo	应用领域
冲电气 - OKI		先进先出芯片
页数	文件大小	规格书
22页	111K
描述
Dual FIFO (262,214-word x 8-Bits) x 2

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MS81V04160 数据手册

OKI Semiconductor

MS81V04160

REVISION1 1999.4.15

Dual FIFO (262,214-word x 8-Bits) x 2

GENERAL DESCRIPTION

The MS81V04160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO

(First-In First-Out) memories which were designed for 256k x 8-bit high-speed

asynchronous read/write operation.

The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in

common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory

(MSM51V8222A), can be used as a x16 configuration FIFO.

The MS81V04160 is a field memory for wide or low end use in general commodity TVs and

VTRs exclusively and is not designed for high end use in professional graphics systems,

which require long term picture storage, data storage, medical use and other storage

systems.

The MS81V04160 provides independent control clocks to support asynchronous read and

write operations. Different clock rates are also supported, which allow alternate data rates

between write and read data streams.

The MS81V04160 provides high speed FIFO (First-in First-out) operation without external

refreshing: MS81V04160 refreshes its DRAM storage cells automatically, so that it appears

fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable the refresh

free serial access operation, so that serial read and/or write control clock can be halted

high or low for any duration as long as the power is on. Internal conflicts of memory access

and refreshing operations are prevented by special arbitration logic.

The MS81V04160’s function is simple, and similar to a digital delay device whose delay-bit-

length is easily set by reset timing. The delay length and the number of read delay clocks

between write and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable

high speed first-bit-access with no clock delay just after the write or read reset timings.

Additionally, the MS81V04160 has a write mask function or input enable function (IE), and

read- data skipping function or output enable function (OE). The differences between write

enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE)

are that WE and RE can stop serial write/read address increments, but IE and OE cannot

stop the increment, when write/read clocking is continuously applied to MS81V04160. The

input enable (IE) function allows the user to write into selected locations of the memory

only, leaving the rest of the memory contents unchanged.This facilitates data processing to

display a “picture in picture” on a TV screen.

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与MS81V04160相关器件

型号	品牌	获取价格	描述	数据表
MS81V04160-25TB	OKI	获取价格	Dual FIFO (262,214-word x 8-Bits) x 2
MS81V04160-30TB	OKI	获取价格	Dual FIFO (262,214-word x 8-Bits) x 2
MS81V04160A	OKI	获取价格	Dual FIFO (262,214 Words 】 8 Bits) 】 2
MS81V04160A-20TB	OKI	获取价格	Dual FIFO (262,214 Words 】 8 Bits) 】 2
MS81V04160A-25TB	OKI	获取价格	Dual FIFO (262,214 Words 】 8 Bits) 】 2
MS81V04166	OKI	获取价格	Dual FIFO (262,214 Words × 8 Bits) × 2
MS81V04166-30TB	OKI	获取价格	FIFO, 256KX8, 30ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS81V04166-40TB	OKI	获取价格	FIFO, 256KX8, 35ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1
MS81V04166A	OKI	获取价格	Dual FIFO (262,214 Words × 8 Bits) × 2
MS81V04166A-20TB	OKI	获取价格	FIFO, 256KX8, 18ns, Synchronous, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-1

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