3.3 V Zero Delay Buffer
MPC962308
NRND
DATASHEET
NRND – Not Recommend for New Designs
The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high-
speed clocks in PC, workstation, datacom, telecom and other high-performance
applications. The MPC962308 uses an internal PLL and an external feedback
path to lock its low-skew clock output phase to the reference clock phase,
providing virtually zero propagation delay. The input-to-output skew is
guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be
less than 200 ps.
MPC962308
Features
D SUFFIX
16-LEAD SOIC PACKAGE
CASE 751B-05
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1:8 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
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Multiple Configurations, see Table 2
Multiple low-skew outputs
200 ps max output-output skew
700 ps max device-device skew
Two banks of four outputs, output tristate control by two select inputs
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H)
±250 ps static phase offset (SPO)
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
16-pin SOIC package or 16-pin TSSOP package
Single 3.3 V supply
Ambient temperature range: –40C to +85C
Compatible with the CY2308 and CY23S08
Spread spectrum compatible
Not Recommend for New Designs
Use replacement part IDT2308
The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Bank
B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the
output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising edges
on the REF input. During this state, all of the outputs are in tristate and there is less than 50 A of current draw. The PLL shuts
down in two additional cases explained in Table 1.
Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the
difference between the output skews of two devices will be less than 700 ps.
The MPC962308 is available in five different configurations as shown in Table 2. In the MPC962308-1, the reference frequency
is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available
to provide faster rise and fall times of the device.
The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides
4X and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different
configurations of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a
high drive version with outputs of REF/2.
The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS
signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on
the incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.
MPC962308 REVISION 4 JANUARY 8, 2013
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©2013 Integrated Device Technology, Inc.