MPC9230EI

更新时间： 2024-11-04 13:11:47

品牌	Logo	应用领域
艾迪悌 - IDT		时钟
页数	文件大小	规格书
16页	795K
描述
Clock Generator, 750MHz, PQCC28, LEAD FREE, PLASTIC, LCC-28

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MPC9230EI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	LEAD FREE, PLASTIC, LCC-28	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.19
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e3
长度：	11.505 mm	湿度敏感等级：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	750 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	20 MHz
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Clock Generators	最大压摆率：	110 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	11.505 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

MPC9230EI 数据手册

800MHz Low Voltage PECL Clock Synthesizer

MPC9230

DATA SHEET

The MPC9230 is a 3.3 V compatible, PLL based clock synthesizer targeted for high perfor-

mance clock generation in mid-range to high-performance telecom, networking and computing

applications. With output frequencies from 50 MHz to 800 MHz⁽¹⁾and the support of differential

PECL output signals the device meets the needs of the most demanding clock applications.

MPC9230

Features

800 MHz LOW VOLTAGE

•

50 MHz to 800 MHz⁽¹⁾synthesized clock output signal

Differential PECL output

CLOCK SYNTHESIZER

LVCMOS compatible control inputs

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference clock input

3.3 V power supply

Fully integrated PLL

Minimal frequency overshoot

Serial 3-wire programming interface

Parallel programming interface for power-up

32-lead LQFP and 28-lead PLCC packaging

32-lead and 28-lead Pb-free package available

SiGe Technology

Ambient temperature range -40°C to +85°C

Pin and function compatible to the MC12430

FN SUFFIX

28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX

28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE

CASE 776-02

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal

oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz.⁽¹⁾Its output is

scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency f_XTAL, the PLL feedback-divider

M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M/4 times the external input reference frequency.

Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is

within the specified VCO frequency range (800 to 1600 MHz⁽¹⁾). The M-value must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4,

or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output

divider, and is capable of driving a pair of transmission lines terminated 50 Ω to V_CC– 2.0 V. The positive supply voltage for the internal PLL

is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure

the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH

transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are

provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial

input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will

capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The

TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL

jitter, it is recommended to avoid active signal on the TEST output.

1. The VCO frequency range of 800–1600 MHz is available at an ambient temperature range of 0 to 70°C. At –40 to +85°C, the VCO frequency (output

frequency) is limited to max. 1500 MHz (750 MHz).

MPC9230 REVISION 8 MARCH 29, 2010

12 3 4 5 6 7...16

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与MPC9230EI相关器件

型号	品牌	获取价格	描述	数据表
MPC9230FA	MOTOROLA	获取价格	800MHz, OTHER CLOCK GENERATOR, PQFP32, LQFP-32
MPC9230FAR2	MOTOROLA	获取价格	800MHz, OTHER CLOCK GENERATOR, PQFP32, LQFP-32
MPC9230FNR2	MOTOROLA	获取价格	Clock Generator, 800MHz, CMOS, PQCC28, PLASTIC, LCC-28
MPC9239	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239AC	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239EI	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer
MPC9239EI	NXP	获取价格	900 MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28
MPC9239EIR2	NXP	获取价格	900MHz, OTHER CLOCK GENERATOR, PQCC28, LEAD FREE, PLASTIC, LCC-28
MPC9239FA	MOTOROLA	获取价格	Clock Generator, 900MHz, CMOS, PQFP32, LQFP-32
MPC9239FA	FREESCALE	获取价格	900 MHz Low Voltage LVPECL Clock Synthesizer

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