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MPC745BZT300RD PDF预览

MPC745BZT300RD

更新时间: 2024-11-11 15:44:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 外围集成电路
页数 文件大小 规格书
2页 509K
描述
RISC Microprocessor, 32-Bit, 300MHz, CMOS, PBGA255, PLASTIC, BGA-255

MPC745BZT300RD 技术参数

生命周期:Obsolete包装说明:BGA,
Reach Compliance Code:unknown风险等级:5.72
地址总线宽度:32位大小:32
边界扫描:NO外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-PBGA-B255长度:23 mm
低功率模式:YES端子数量:255
最高工作温度:105 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:2.6 mm速度:300 MHz
标称供电电压:2 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:23 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

MPC745BZT300RD 数据手册

 浏览型号MPC745BZT300RD的Datasheet PDF文件第2页 
MPC755FACT/D  
REV. 0  
F a c t S h e e t  
MO T O R O L A MPC755 A N D MPC745  
PO W E R PC MI C R O P R O C E S S O R S  
MPC755 and MPC745 PowerPC microprocessors are high-performance, low-power, 32-bit implementations of  
the PowerPC Reduced Instruction Set Computer (RISC) architecture, specially enhanced for embedded applications.  
MPC755 and MPC745 microprocessors differ only in that the MPC755 features an enhanced, dedicated L2 cache  
interface with on-chip L2 tags. The MPC755 is a drop-in replacement for the award winning PowerPC 750™  
microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec  
™ technology. The MPC745 is a drop-in replacement for the PowerPC 740™ microprocessor and is also footprint  
and user software code compatible with the PowerPC 603e™  
microprocessor. MPC755/745 microprocessors provide on-chip  
debug support and are fully JTAG-compliant.  
Motorola MPC755  
PowerPC Microprocessor  
Superscalar Microprocessor  
MPC755 and MPC745 microprocessors are superscalar, capable  
of issuing three instructions per clock cycle (two instructions  
+ branch) into six independent execution units:  
Two integer units  
Load/store unit  
Double-precision floating-point unit  
System register unit  
Branch processing unit  
The ability to execute multiple instructions in parallel, to  
MPC755/745 Microprocessor  
Block Diagram  
pipeline instructions, and the use of simple instructions  
with rapid execution times yields maximum efficiency and  
throughput for MPC755 and MPC745 systems.  
Completion  
Unit  
Branch  
Unit  
Dispatch  
Unit  
Power Management  
The MPC755 and MPC745 microprocessors feature a  
low-power 2.0-volt design with three power-saving user-  
programmable modes — doze, nap and sleep — which  
progressively reduce the power drawn by the processor.  
Load/  
Store  
Unit  
Floating  
Point  
Unit  
Gen  
Reg  
File  
FPU  
Reg  
File  
D MMU  
I MMU  
Data Cache  
Inst. Cache  
These low-power microprocessors offer dynamic power  
management to selectively activate functional units as they  
are needed by the executing instructions. Both  
microprocessors also provide a thermal assist unit and  
instruction cache throttling for software-controllable  
thermal management.  
Bus Interface Unit  
L2 Tags  
L2 Cache  
Port (755 only)  
32b Address  
32b/64b Data  
System Bus  
FSRAM  

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