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MMDP-65656L-55/883 PDF预览

MMDP-65656L-55/883

更新时间: 2024-11-12 14:53:51
品牌 Logo 应用领域
TEMIC 静态存储器内存集成电路
页数 文件大小 规格书
9页 105K
描述
Standard SRAM, 32KX8, 55ns, CMOS, CQFP28,

MMDP-65656L-55/883 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.86
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-CQFP-F28JESD-609代码:e0
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:32KX8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装等效代码:FL28,.4封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
最大待机电流:0.0003 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.09 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

MMDP-65656L-55/883 数据手册

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MATRA MHS  
M 65656  
32 K × 8 Ultimate CMOS SRAM  
Description  
The M 65656 is a very low power CMOS static RAM current (Typical value = 0.1 µA) with a fast access time  
organized as 32768 × 8 bits. It is manufactured using the at 40 ns. The high stability of the 6T cell provides  
MHS high performance CMOS technology named excellent protection against soft errors due to noise.  
SCMOS.  
Extra protection against heavy ions is given by the use of  
With this process, MHS is the first to bring the solution for  
applications where fast computing is as mandatory as low  
consumption, such as aerospace electronics, portable  
instruments or embarked systems.  
an epitaxial layer of a P substrate.  
For military/space applications that demand superior  
levels of performance and reliability the M 65656 is  
processed according to the methods of the latest revision  
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.  
Using an array of six transistors (6T) memory cells, the  
M 65656 combines an extremely low standby supply  
Features  
D Access time  
D Wide temperature range : –55 to + 125°C  
D 300 and 600 mils width package  
D TTL compatible inputs and outputs  
D Asynchronous  
commercial : 35(*), 40, 45, 55 ns  
industrial automotive and military : 40(*), 45, 55 ns  
D Very low power consumption  
active : 50 mW (typ)  
D Single 5 volt supply  
D Equal cycle and access time  
standby : 0.5 µW (typ)  
data retention : 0.4 µW (typ)  
(*) Preliminary. Consult sales.  
D Gated inputs :  
no pull-up/down  
resistors are required  
Interface  
Block Diagram  
Rev. C (09/08/95)  
1

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