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MM80C95 PDF预览

MM80C95

更新时间: 2024-11-03 22:07:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 86K
描述
3-STATE Hex Buffers 3-STATE Hex Inverters

MM80C95 数据手册

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October 1987  
Revised January 1999  
MM80C95 • MM80C97 • MM80C98  
3-STATE Hex Buffers • 3-STATE Hex Inverters  
General Description  
Features  
The MM80C95, MM80C97 and MM80C98 gates are mono-  
lithic complementary MOS (CMOS) integrated circuits con-  
structed with N- and P-channel enhancement mode  
transistors. The MM80C95 and the MM80C97 convert  
CMOS or TTL outputs to 3-STATE outputs with no logic  
inversion, the MM80C98 provides the logical opposite of  
the input signal. The MM80C95 has common 3-STATE  
controls for all six devices. The MM80C97 and the  
MM80C98 have two 3-STATE controls; one for two devices  
and one for the other four devices. Inputs are protected  
from damage due to static discharge by diode clamps to  
VCC and GND.  
Wide supply voltage range: 3.0V to 15V  
Guaranteed noise margin: 1.0V  
High noise immunity: 0.45 VCC (typ.)  
TTL compatible: Drive 1 TTL Load  
Applications  
Bus drivers: Typical propagation delay into 150 pF load  
is 40 ns  
Ordering Code:  
Order Number Package Number  
Package Description  
MM80C95N  
MM80C97M  
MM80C97N  
MM80C98N  
N16E  
M16A  
N16E  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP  
MM80C95  
MM80C97  
Top View  
Top View  
MM80C98  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005907.prf  
www.fairchildsemi.com  

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