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MM74HCT541

更新时间: 2024-11-19 23:02:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 95K
描述
Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer

MM74HCT541 数据手册

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February 1984  
Revised February 1999  
MM74HCT540 • MM74HCT541  
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer  
The MM74HCT540 is an inverting buffer and the  
MM74HCT541 is a non-inverting buffer. The 3-STATE con-  
General Description  
The MM74HCT540 and MM74HCT541 3-STATE buffers  
trol gate operates as a two-input NOR such that if either G1  
utilize advanced silicon-gate CMOS technology and are  
or G2 are HIGH, all eight outputs are in the high-imped-  
general purpose high speed inverting and non-inverting  
ance state.  
buffers. They possess high drive current outputs which  
In order to enhance PC board layout, the MM74HCT540  
enable high speed operation even when driving large bus  
and MM74HCT541 offers a pinout having inputs and out-  
capacitances. These circuits achieve speeds comparable  
puts on opposite sides of the package. All inputs are pro-  
to low power Schottky devices, while retaining the low  
tected from damage due to static discharge by diodes to  
power consumption of CMOS. Both devices are TTL input  
VCC and ground.  
compatible and have a fanout of 15 LS-TTL equivalent  
inputs.  
Features  
TTL input compatible  
MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices.  
These parts are also plug-in replacements for LS-TTL  
devices and can be used to reduce power consumption in  
existing designs.  
Typical propagation delay: 12 ns  
3-STATE outputs for connection to system buses  
Low quiescent current: 80 µA  
Output current: 6 mA (min.)  
Ordering Code:  
Order Number  
MM74HCT540WM  
MM74HCT540SJ  
MM74HCT540MTC  
MM74HCT540N  
MM74HCT541WM  
MM74HCT541SJ  
MM74HCT541MTC  
MM74HCT541N  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20B  
M20D  
MTC20  
N20A  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Top View  
MM74HCT540  
Top View  
MM74HCT541  
© 1999 Fairchild Semiconductor Corporation  
DS006040.prf  
www.fairchildsemi.com  

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