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MM74HCT193N PDF预览

MM74HCT193N

更新时间： 2024-02-14 18:45:51
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 150K
描述
Synchronous Binary Up/Down Counters

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中文翻译

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MM74HCT193N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.34
其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK计数方向：BIDIRECTIONAL
系列：HCTJESD-30 代码：R-PDIP-T16
JESD-609代码：e0长度：19.305 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：16000000 Hz
最大I（ol）：0.004 A工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：54 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：16 MHz
Base Number Matches：1

MM74HCT193N 数据手册

 浏览型号MM74HCT193N的Datasheet PDF文件第2页浏览型号MM74HCT193N的Datasheet PDF文件第3页浏览型号MM74HCT193N的Datasheet PDF文件第4页浏览型号MM74HCT193N的Datasheet PDF文件第5页浏览型号MM74HCT193N的Datasheet PDF文件第6页浏览型号MM74HCT193N的Datasheet PDF文件第7页 
January 1988  
MM54HCT193/MM74HCT193  
Synchronous Binary Up/Down Counters  
General Description  
These high speed synchronous counters utilize advanced  
silicon-gate CMOS technology to achieve the high noise im-  
munity and low power consumption of CMOS technology,  
along with the speeds of low power Schottky TTL. The  
MM54HCT193/MM74HCT193 is a binary counter having  
two separate clock inputs, an UP COUNT input and a  
DOWN COUNT input. All outputs of the flip-flops are simul-  
taneously triggered on the low-to-high transition of either  
clock while the other input is held high. The direction of  
counting is determined by which input is clocked.  
Both a BORROW and CARRY output are provided to en-  
able cascading of both up and down counting functions. The  
BORROW output produces a negative-going pulse when  
the counter underflows and the CARRY outputs a pulse  
when the counter overflows. The counter can be cascaded  
by connecting the CARRY and BORROW outputs of one  
device to the COUNT UP and COUNT DOWN inputs, re-  
spectively, of the next device.  
All inputs are protected from damage due to static dis-  
charge by diodes to V  
and ground.  
CC  
This device has TTL compatible inputs. It can drive 15 LS-  
TTL loads.  
Features  
Y
This counter may be preset by entering the desired data on  
the DATA A, DATA B, DATA C, and DATA D inputs. When  
the LOAD input is taken low, the data is loaded indepen-  
dently of either clock input. This feature allows the counter  
to be used as a divide-by-n counter by modifying the count  
length with the preset inputs.  
Low quiescent supply current: 80 mA maximum (74HCT  
Series)  
Y
Y
Low input current: 1 mA maximum  
TTL compatible inputs  
In addition, the HCT193 can also be cleared. This is accom-  
plished by inputting a high on the CLEAR input. All 4 internal  
stages are set to a low level independently of either COUNT  
input.  
Connection Diagram  
Truth Table  
Dual-In-Line Package  
Count  
Clear  
Load  
Function  
Up  
Down  
H
u
X
L
L
H
H
X
L
Count Up  
Count Down  
Clear  
u
H
X
H
L
X
X
Load  
e
H
L
high level  
e
e
e
low level  
transition from low-to-high  
don’t care  
u
X
TL/F/5742–1  
Order Number MM54HCT193 or MM74HCT193  
C
1995 National Semiconductor Corporation  
TL/F/5742  
RRD-B30M105/Printed in U. S. A.  
1234567...9

中文翻译

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MM74HCT240J/A+ NSC

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