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MM74HCT05N PDF预览

MM74HCT05N

更新时间: 2024-11-19 22:40:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 83K
描述
Hex Inverter (Open Drain)

MM74HCT05N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.16
系列:HCTJESD-30 代码:R-PDIP-T14
JESD-609代码:e3长度:19.18 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.004 A功能数量:6
输入次数:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:5 V
Prop。Delay @ Nom-Sup:28 ns传播延迟(tpd):28 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

MM74HCT05N 数据手册

 浏览型号MM74HCT05N的Datasheet PDF文件第2页浏览型号MM74HCT05N的Datasheet PDF文件第3页浏览型号MM74HCT05N的Datasheet PDF文件第4页浏览型号MM74HCT05N的Datasheet PDF文件第5页浏览型号MM74HCT05N的Datasheet PDF文件第6页 
February 1984  
Revised February 1999  
MM74HCT05  
Hex Inverter (Open Drain)  
These parts are also plug-in replacements for LS-TTL  
devices and can be used to reduce power consumption in  
existing designs.  
General Description  
The MM74HCT05 is a logic function fabricated by using  
advanced silicon-gate CMOS technology, which provides  
the inherent benefits of CMOS—low quiescent power and  
wide power supply range. The device is also input and out-  
put characteristic and pinout compatible with standard  
DM74LS logic families. The MM74HCT05 open drain Hex  
Inverter requires the addition of an external resistor to per-  
form a wire-NOR function.  
Features  
Open drain for wire-NOR function  
LS-TTL pinout and threshold compatible  
Fanout of 10 LS-TTL loads  
Typical propagation delays:  
All inputs are protected from static discharge damage by  
internal diodes to VCC and ground.  
tPLH (with 1 kresistor) 10 ns  
tPHL (with 1 kresistor) 8 ns  
MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices.  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HCT05M  
MM74HCT05SJ  
MM74HCT05MTC  
MM74HCT05N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Typical Application  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005358.prf  
www.fairchildsemi.com  

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