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MM74HCT00SJX_NL PDF预览

MM74HCT00SJX_NL

更新时间: 2024-11-20 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
6页 82K
描述
NAND Gate, HCT Series, 4-Func, 2-Input, CMOS, PDSO14, 5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-14

MM74HCT00SJX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:29 ns
传播延迟(tpd):29 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

MM74HCT00SJX_NL 数据手册

 浏览型号MM74HCT00SJX_NL的Datasheet PDF文件第2页浏览型号MM74HCT00SJX_NL的Datasheet PDF文件第3页浏览型号MM74HCT00SJX_NL的Datasheet PDF文件第4页浏览型号MM74HCT00SJX_NL的Datasheet PDF文件第5页浏览型号MM74HCT00SJX_NL的Datasheet PDF文件第6页 
February 1984  
Revised February 1999  
MM74HCT00  
Quad 2 Input NAND Gate  
These parts are also plug-in replacements for LS-TTL  
devices and can be used to reduce power consumption in  
existing designs.  
General Description  
The MM74HCT00 is  
a NAND gates fabricated using  
advanced silicon-gate CMOS technology which provides  
the inherent benefits of CMOS—low quiescent power and  
wide power supply range. This device is input and output  
characteristic and pin-out compatible with standard 74LS  
logic families. All inputs are protected from static discharge  
damage by internal diodes to VCC and ground.  
Features  
TTL, LS pin-out and threshold compatible  
Fast switching: tPLH, tPHL=14 ns (typ)  
Low power: 10 µW at DC  
MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices.  
High fan out, 10 LS-TTL loads  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HCT00M  
MM74HCT00SJ  
MM74HCT00MTC  
MM74HCT00N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrate Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
(1 of 4 gates)  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005356.prf  
www.fairchildsemi.com  

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