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MM74HC86SJX PDF预览

MM74HC86SJX

更新时间: 2024-11-19 21:53:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路石英晶振光电二极管
页数 文件大小 规格书
7页 84K
描述
Quad 2-Input Exclusive OR Gate

MM74HC86SJX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOP
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.1
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:30 ns
传播延迟(tpd):151 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.1 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

MM74HC86SJX 数据手册

 浏览型号MM74HC86SJX的Datasheet PDF文件第2页浏览型号MM74HC86SJX的Datasheet PDF文件第3页浏览型号MM74HC86SJX的Datasheet PDF文件第4页浏览型号MM74HC86SJX的Datasheet PDF文件第5页浏览型号MM74HC86SJX的Datasheet PDF文件第6页浏览型号MM74HC86SJX的Datasheet PDF文件第7页 
September 1983  
Revised January 2005  
MM74HC86  
Quad 2-Input Exclusive OR Gate  
General Description  
Features  
The MM74HC86 EXCLUSIVE OR gate utilizes advanced  
silicon-gate CMOS technology to achieve operating  
speeds similar to equivalent LS-TTL gates while maintain-  
ing the low power consumption and high noise immunity  
characteristic of standard CMOS integrated circuits. These  
gates are fully buffered and have a fanout of 10 LS-TTL  
loads. The 74HC logic family is functionally as well as pin  
out compatible with the standard 74LS logic family. All  
inputs are protected from damage due to static discharge  
by internal diode clamps to VCC and ground.  
Typical propagation delay: 9 ns  
Wide operating voltage range: 2–6V  
Low input current: 1 µA maximum  
Low quiescent current: 20 µA maximum (74 Series)  
Output drive capability: 10 LS-TTL loads  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
MM74HC86M  
M14A  
M14A  
M14D  
MTC14  
N14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
MM74HC86MX_NL  
MM74HC86SJ  
MM74HC86MTC  
MM74HC86N  
MM74HC86NX_NL  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Truth Table  
Inputs  
Outputs  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
A
L
B
L
Y
L
L
H
L
H
H
L
H
H
H
Y = A B = A B + AB  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005305  
www.fairchildsemi.com  

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