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MM74HC86MTCX_NL PDF预览

MM74HC86MTCX_NL

更新时间: 2024-11-20 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
7页 84K
描述
XOR Gate, HC/UH Series, 4-Func, 2-Input, CMOS, PDSO14, 4.40 MM, LEAD FREE, MO-153, TSSOP-14

MM74HC86MTCX_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, LEAD FREE, MO-153, TSSOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e3/e4
长度:5 mm逻辑集成电路类型:XOR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):151 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN/NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

MM74HC86MTCX_NL 数据手册

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September 1983  
Revised January 2005  
MM74HC86  
Quad 2-Input Exclusive OR Gate  
General Description  
Features  
The MM74HC86 EXCLUSIVE OR gate utilizes advanced  
silicon-gate CMOS technology to achieve operating  
speeds similar to equivalent LS-TTL gates while maintain-  
ing the low power consumption and high noise immunity  
characteristic of standard CMOS integrated circuits. These  
gates are fully buffered and have a fanout of 10 LS-TTL  
loads. The 74HC logic family is functionally as well as pin  
out compatible with the standard 74LS logic family. All  
inputs are protected from damage due to static discharge  
by internal diode clamps to VCC and ground.  
Typical propagation delay: 9 ns  
Wide operating voltage range: 2–6V  
Low input current: 1 µA maximum  
Low quiescent current: 20 µA maximum (74 Series)  
Output drive capability: 10 LS-TTL loads  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
MM74HC86M  
M14A  
M14A  
M14D  
MTC14  
N14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
MM74HC86MX_NL  
MM74HC86SJ  
MM74HC86MTC  
MM74HC86N  
MM74HC86NX_NL  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Truth Table  
Inputs  
Outputs  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
A
L
B
L
Y
L
L
H
L
H
H
L
H
H
H
Y = A B = A B + AB  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005305  
www.fairchildsemi.com  

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