MM74HC533J

更新时间： 2024-11-03 10:53:03

品牌	Logo	应用领域
美国国家半导体 - NSC		总线驱动器总线收发器锁存器逻辑集成电路
页数	文件大小	规格书
4页	97K
描述
TRI-STATE-R Octal D-Type Latch with Inverted Outputs

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MM74HC533J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
风险等级：	5.38	系列：	HC/UH
JESD-30 代码：	R-GDIP-T20	JESD-609代码：	e0
长度：	24.51 mm	负载电容（CL）：	150 pF
逻辑集成电路类型：	BUS DRIVER	最大I（ol）：	0.006 A
位数：	8	功能数量：	1
端口数量：	2	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	输出极性：	INVERTED
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2/6 V	Prop。Delay @ Nom-Sup：	37 ns
传播延迟（tpd）：	56 ns	认证状态：	Not Qualified
座面最大高度：	5.08 mm	子类别：	FF/Latches
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	7.62 mm
Base Number Matches：	1

MM74HC533J 数据手册

January 1988

MM54HC533/MM74HC533

TRI-STATE Octal D-Type Latch

with Inverted Outputs

General Description

These high speed OCTAL D-TYPE LATCHES utilize ad-

vanced silicon-gate CMOS technology. They possess the

high noise immunity and low power consumption of stan-

dard CMOS integrated circuits, as well as the ability to drive

15 LS-TTL loads. Due to the large output drive capability

and the TRI-STATE feature, these devices are ideally suited

for interfacing with bus lines in a bus organized system.

The 54HC/74HC logic family is speed, function, and pin-out

compatible with the standard 54LS/74LS logic family. All

inputs are protected from damage due to static discharge by

internal diode clamps to V

and ground.

Features

Typical propagation delay: 18 ns

When the LATCH ENABLE input is high, the data present

on the D inputs will appear inverted at the Q outputs. When

the LATCH ENABLE goes low, the inverted data will be re-

tained at the Q outputs until LATCH ENABLE returns high

again. When a high logic level is applied to the OUTPUT

CONTROL input, all outputs go to a high impedance state,

regardless of what signals are present at the other inputs

and the state of the storage elements.

Wide operating voltage range: 2 to 6 volts

Low input current: 1 mA maximum

Low quiescent current: 80 mA, maximum (74HC Series)

Compatible with bus-oriented systems

Output drive capability: 15 LS-TTL loads

Connection Diagram

Dual-In-Line Package

TL/F/5339–1

Top View

Order Number MM54HC533 or MM74HC533

Truth Table

Latch

Enable

Output

Control

low level

high level, L

Data

Output

level of output before steady-state input conditions

were established.

high impedance

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/F/5339

RRD-B30M105/Printed in U. S. A.

12 3 4

中文翻译

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与MM74HC533J相关器件

型号	品牌	获取价格	描述	数据表
MM74HC533N	NSC	获取价格	TRI-STATE-R Octal D-Type Latch with Inverted Outputs
MM74HC533WM/A+	NSC	获取价格	IC,LATCH,SINGLE,8-BIT,HC-CMOS,SOP,20PIN,PLASTIC
MM74HC533WMX	TI	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20
MM74HC534J	TI	获取价格	HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20
MM74HC534J	NSC	获取价格	IC HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20, Bus Driver/Transc
MM74HC534J	FAIRCHILD	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, CDIP20
MM74HC534J/A+	TI	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,DIP,20PIN,CERAMIC
MM74HC534N	FAIRCHILD	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, PDIP20
MM74HC534N	NSC	获取价格	IC HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20, PLASTIC, DIP-20, Bus Driver/Transc
MM74HC534N/A+	TI	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,DIP,20PIN,PLASTIC

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