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MM74HC51J/A+ PDF预览

MM74HC51J/A+

更新时间: 2024-11-03 13:02:23
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
4页 129K
描述
IC,LOGIC GATE,2/2-INPUT AND-NOR,HC-CMOS,DIP,14PIN,CERAMIC

MM74HC51J/A+ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0逻辑集成电路类型:AND-OR-INVERT GATE
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V施密特触发器:NO
子类别:Gates表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MM74HC51J/A+ 数据手册

 浏览型号MM74HC51J/A+的Datasheet PDF文件第2页浏览型号MM74HC51J/A+的Datasheet PDF文件第3页浏览型号MM74HC51J/A+的Datasheet PDF文件第4页 
January 1988  
MM54HC51/MM74HC51 Dual AND-OR-Invert Gate  
MM54HC58/MM74HC58 Dual AND-OR Gate  
General Description  
Features  
Y
Typical propagation delay: 10 ns  
These gates utilize advanced silicon-gate CMOS technology  
to achieve operating speeds similar to LS-TTL gates with  
the low power consumption of standard CMOS integrated  
circuits. All gates have buffered outputs, providing high  
noise immunity and the ability to drive 10 LS-TTL loads. The  
54HC/74HC logic family is functionally as well as pin-out  
compatible with the standard 54LS/74LS logic family. All  
inputs are protected from damage due to static discharge by  
Y
Wide power supply range: 26V  
Y
Low quiescent supply current: 20 mA maximum  
(74 Series)  
Y
Y
Low input current: 1 mA maximum  
High output current: 4 mA minimum  
internal diode clamps to V  
and ground.  
CC  
Connection Diagrams  
Dual-In-Line Package  
TL/F/5302–1  
Top View  
Order Number MM54HC51 or MM74HC51  
Dual-In-Line Package  
TL/F/5302–2  
Top View  
Order Number MM54HC58 or MM74HC58  
C
1995 National Semiconductor Corporation  
TL/F/5302  
RRD-B30M105/Printed in U. S. A.  

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