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MM74HC4050J PDF预览

MM74HC4050J

更新时间: 2024-11-26 13:01:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 72K
描述
Buffer, HC/UH Series, 6-Func, 1-Input, CMOS, CDIP16, DIP-16

MM74HC4050J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.43系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.43 mm
逻辑集成电路类型:BUFFER功能数量:6
输入次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):100 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MM74HC4050J 数据手册

 浏览型号MM74HC4050J的Datasheet PDF文件第2页浏览型号MM74HC4050J的Datasheet PDF文件第3页浏览型号MM74HC4050J的Datasheet PDF文件第4页浏览型号MM74HC4050J的Datasheet PDF文件第5页浏览型号MM74HC4050J的Datasheet PDF文件第6页 
February 1984  
Revised October 1999  
MM74HC4049 • MM74HC4050  
Hex Inverting Logic Level Down Converter •  
Hex Logic Level Down Converter  
ple buffer or inverter without level translation. The  
MM74HC4049 is pin and functionally compatible to the  
CD4049BC and the MM74HC4050 is compatible to the  
CD4050BC  
General Description  
The MM74HC4049 and the MM74HC4050 utilize  
advanced silicon-gate CMOS technology, and have a mod-  
ified input protection structure that enables these parts to  
be used as logic level translators which will convert high  
level logic to a low level logic while operating from the low  
logic supply. For example, 0–15V CMOS logic can be con-  
verted to 0–5V logic when using a 5V supply. The modified  
input protection has no diode connected to VCC, thus allow-  
Features  
Typical propagation delay: 8 ns  
Wide power supply range: 2V–6V  
Low quiescent supply current: 20 µA maximum (74HC)  
Fanout of 10 LS-TTL loads  
ing the input voltage to exceed the supply. The lower zener  
diode protects the input from both positive and negative  
static voltages. In addition each part can be used as a sim-  
Ordering Code:  
Order Number  
Package Number Package Description  
MM74HC4049M  
MM74HC4049SJ  
MM74HC4049MTC  
MM74HC4049N  
MM74HC4050M  
MM74HC4050SJ  
MM74HC4050MTC  
MM74HC4050N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M16A  
M16D  
MTC16  
N16E  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagrams  
MM74HC4049  
MM74HC4050  
© 1999 Fairchild Semiconductor Corporation  
DS005214  
www.fairchildsemi.com  

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