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MM74HC4046N PDF预览

MM74HC4046N

更新时间: 2024-11-25 23:02:43
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
17页 252K
描述
CMOS Phase Lock Loop

MM74HC4046N 数据手册

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February 1984  
Revised October 2003  
MM74HC4046  
CMOS Phase Lock Loop  
them. This comparator is more susceptible to noise throw-  
ing the loop out of lock, but is less likely to lock onto har-  
monics than the other two comparators.  
General Description  
The MM74HC4046 is a low power phase lock loop utilizing  
advanced silicon-gate CMOS technology to obtain high fre-  
quency operation both in the phase comparator and VCO  
sections. This device contains a low power linear voltage  
controlled oscillator (VCO), a source follower, and three  
phase comparators. The three phase comparators have a  
common signal input and a common comparator input. The  
signal input has a self biasing amplifier allowing signals to  
be either capacitively coupled to the phase comparators  
with a small signal or directly coupled with standard input  
logic levels. This device is similar to the CD4046 except  
that the Zener diode of the metal gate CMOS device has  
been replaced with a third phase comparator.  
In a typical application any one of the three comparators  
feed an external filter network which in turn feeds the VCO  
input. This input is a very high impedance CMOS input  
which also drives the source follower. The VCO’s operating  
frequency is set by three external components connected  
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided  
to disable the VCO and the source follower, providing a  
method of putting the IC in a low power state.  
The source follower is a MOS transistor whose gate is con-  
nected to the VCO input and whose drain connects the  
Demodulator output. This output normally is used by tying  
a resistor from pin 10 to ground, and provides a means of  
looking at the VCO input without loading down modifying  
the characteristics of the PLL filter.  
Phase Comparator I is an exclusive OR (XOR) gate. It pro-  
vides a digital error signal that maintains a 90 phase shift  
between the VCO’s center frequency and the input signal  
(50% duty cycle input waveforms). This phase detector is  
more susceptible to locking onto harmonics of the input fre-  
quency than phase comparator I, but provides better noise  
rejection.  
Features  
Low dynamic power consumption: (VCC = 4.5V)  
Maximum VCO operating frequency:  
12 MHz (VCC = 4.5V)  
Phase comparator III is an SR flip-flop gate. It can be used  
to provide the phase comparator functions and is similar to  
the first comparator in performance.  
Fast comparator response time (VCC = 4.5V)  
Comparator I: 25 ns  
Phase comparator II is an edge sensitive digital sequential  
network. Two signal outputs are provided, a comparator  
output and a phase pulse output. The comparator output is  
a 3-STATE output that provides a signal that locks the VCO  
output signal to the input signal with 0 phase shift between  
Comparator II: 30 ns  
Comparator III: 25 ns  
VCO has high linearity and high temperature stability  
Ordering Code:  
Order Number  
MM74HC4046M  
MM74HC4046SJ  
MM74HC4046MTC  
MM74HC4046N  
Package Number  
M16A  
Package Description  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
M16D  
MTC16  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
© 2003 Fairchild Semiconductor Corporation  
DS005352  
www.fairchildsemi.com  

MM74HC4046N 替代型号

型号 品牌 替代类型 描述 数据表
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CD4046BE TI

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