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MM74HC373MTC PDF预览

MM74HC373MTC

更新时间: 2024-11-02 23:02:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 91K
描述
3-STATE Octal D-Type Latch

MM74HC373MTC 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.09
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:37 ns传播延迟(tpd):280 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MM74HC373MTC 数据手册

 浏览型号MM74HC373MTC的Datasheet PDF文件第2页浏览型号MM74HC373MTC的Datasheet PDF文件第3页浏览型号MM74HC373MTC的Datasheet PDF文件第4页浏览型号MM74HC373MTC的Datasheet PDF文件第5页浏览型号MM74HC373MTC的Datasheet PDF文件第6页浏览型号MM74HC373MTC的Datasheet PDF文件第7页 
September 1983  
Revised February 1999  
MM74HC373  
3-STATE Octal D-Type Latch  
signals are present at the other inputs and the state of the  
storage elements.  
General Description  
The MM74HC373 high speed octal D-type latches utilize  
advanced silicon-gate CMOS technology. They possess  
the high noise immunity and low power consumption of  
standard CMOS integrated circuits, as well as the ability to  
drive 15 LS-TTL loads. Due to the large output drive capa-  
bility and the 3-STATE feature, these devices are ideally  
suited for interfacing with bus lines in a bus organized sys-  
tem.  
The 74HC logic family is speed, function, and pin-out com-  
patible with the standard 74LS logic family. All inputs are  
protected from damage due to static discharge by internal  
diode clamps to VCC and ground.  
Features  
Typical propagation delay: 18 ns  
When the LATCH ENABLE input is HIGH, the Q outputs  
will follow the D inputs. When the LATCH ENABLE goes  
LOW, data at the D inputs will be retained at the outputs  
until LATCH ENABLE returns HIGH again. When a high  
logic level is applied to the OUTPUT CONTROL input, all  
outputs go to a high impedance state, regardless of what  
Wide operating voltage range: 2 to 6 volts  
Low input current: 1 µA maximum  
Low quiescent current: 80 µA maximum (74 Series)  
Output drive capability: 15 LS-TTL loads  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC373WM  
MM74HC373SJ  
MM74HC373MTC  
MM74HC373N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Output  
Latch  
Data  
373  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Control  
Enable  
Output  
L
L
H
H
L
H
L
H
L
L
X
X
Q0  
Z
H
X
H = HIGH Level  
L = LOW Level  
Q
= Level of output before steady-state input conditions were established.  
0
Z = High Impedance  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005335.prf  
www.fairchildsemi.com  

MM74HC373MTC 替代型号

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MM74HC373MTCX FAIRCHILD

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与MM74HC373MTC相关器件

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MM74HC373N FAIRCHILD

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3-STATE Octal D-Type Latch
MM74HC373N ROCHESTER

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8-Bit D-Type Latch
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8-Bit D-Type Latch
MM74HC373N_NL FAIRCHILD

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Bus Driver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, 0.300 INCH, MS-001, PL
MM74HC373SJ FAIRCHILD

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3-STATE Octal D-Type Latch