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MM74HC280J PDF预览

MM74HC280J

更新时间: 2024-11-01 23:02:43
品牌 Logo 应用领域
美国国家半导体 - NSC 运算电路逻辑集成电路
页数 文件大小 规格书
4页 114K
描述
9-Bit Odd/Even Parity Generator/Checker

MM74HC280J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.31
其他特性:ODD/EVEN PARITY GENERATOR系列:HC/UH
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:PARITY GENERATOR/CHECKER
位数:9功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):52 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM74HC280J 数据手册

 浏览型号MM74HC280J的Datasheet PDF文件第2页浏览型号MM74HC280J的Datasheet PDF文件第3页浏览型号MM74HC280J的Datasheet PDF文件第4页 
January 1988  
MM54HC280/MM74HC280  
9-Bit Odd/Even Parity Generator/Checker  
General Description  
Features  
Y
The MM54HC280/MM74HC280 utilizes advanced silicon-  
gate CMOS technology to achieve the high noise immunity  
and low power consumption of standard CMOS integrated  
circuits. It possesses the ability to drive 10 LS-TTL loads.  
Typical propagation delay: 28 ns  
Y
Wide power supply range: 2V6V  
Y
Low quiescent current: 80 mA maximum (74HC)  
Low input current: 1 mA maximum  
Fanout of 10 LS-TTL loads  
Y
Y
This parity generator/checker features odd/even outputs to  
facilitate operation of either odd or even parity applications.  
The word length capability is easily expanded by cascading  
devices. The 54HC/74HC logic family is speed, function,  
and pinout compatible with the standard 54LS/74LS family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Connection Diagram  
Dual-In-Line Package  
TL/F/5121–1  
Order Number MM54HC280 or MM74HC280  
Function Table  
Numbers of Inputs A  
Outputs  
thru 1 that are High  
R Even  
R Odd  
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
H
e
e
low level  
H
high level,  
L
C
1995 National Semiconductor Corporation  
TL/F/5121  
RRD-B30M105/Printed in U. S. A.  

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