September 1983
Revised February 1999
MM74HC139
Dual 2-To-4 Line Decoder
equivalent to the 74LS139. All inputs are protected from
damage due to static discharge by diodes to VCC and
General Description
The MM74HC139 decoder utilizes advanced silicon-gate
CMOS technology, and is well suited to memory address
decoding or data routing applications. It possesses the
high noise immunity and low power consumption usually
associated with CMOS circuitry, yet has speeds compara-
ble to low power Schottky TTL logic.
ground.
Features
■ Typical propagation delays —
Select to outputs (4 delays): 18 ns
Select to output (5 delays): 28 ns
Enable to output: 20 ns
The MM74HC139 contain two independent one-of-four
decoders each with a single active low enable input (G1, or
G2). Data on the select inputs (A1, and B1 or A2, and B2)
cause one of the four normally high outputs to go LOW.
■ Low power: 40 µW quiescent supply power
■ Fanout of 10 LS-TTL devices
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent loads, and are functionally as well as pin
■ Input current maximum 1 µA, typical 10 pA
Ordering Code:
Order Number Package Number
Package Description
MM74HC139M
MM74HC139SJ
MM74HC139MTC
MM74HC139N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP) JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Outputs
Enable
Select
G
H
L
B
A
X
L
Y0
H
L
Y1
H
H
L
Y2
H
H
H
L
Y3
H
H
H
H
L
X
L
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
H = HIGH Level
L = LOW Level
X = Don't Care
© 1999 Fairchild Semiconductor Corporation
DS005311.prf
www.fairchildsemi.com