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MM74HC133N PDF预览

MM74HC133N

更新时间: 2024-11-23 22:46:07
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
4页 143K
描述
13-Input NAND Gate

MM74HC133N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.48
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A功能数量:1
输入次数:13端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:42 ns
传播延迟(tpd):190 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM74HC133N 数据手册

 浏览型号MM74HC133N的Datasheet PDF文件第2页浏览型号MM74HC133N的Datasheet PDF文件第3页浏览型号MM74HC133N的Datasheet PDF文件第4页 
January 1988  
MM54HC133/MM74HC133 13-Input NAND Gate  
General Description  
Features  
Y
Typical propagation delay: 20 ns  
This NAND gate utilizes advanced silicon-gate CMOS tech-  
nology to achieve operating speeds similar to LS-TTL gates  
with the low power consumption of standard CMOS inte-  
grated circuits. All gates have buffered outputs. All devices  
have high noise immunity and the ability to drive 10 LS-TTL  
loads. The 54HC/74HC logic family is functionally as well as  
pin-out compatible with the standard 54LS/74LS logic fami-  
ly. All inputs are protected from damage due to static dis-  
Y
Wide power supply range: 26V  
Y
Low quiescent current: 20 mA maximum (74HC Series)  
Low input current: 1 mA maximum  
Y
Y
Fanout of 10 LS-TTL loads  
charge by internal diode clamps to V  
and ground.  
CC  
Connection and Logic Diagrams  
Dual-In-Line Package  
TL/F/5134–1  
Top View  
Order Number MM54HC133 or MM74HC133  
TL/F/5134–2  
C
1995 National Semiconductor Corporation  
TL/F/5134  
RRD-B30M105/Printed in U. S. A.  

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