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MM74C907N PDF预览

MM74C907N

更新时间: 2024-02-26 18:12:53
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 56K
描述
Hex Open Drain N-Channel Buffers . Hex Open Drain P-Channel Buffers

MM74C907N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N系列:CMOS
JESD-30 代码:R-PDIP-T14JESD-609代码:e0
长度:19.18 mm逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
Prop。Delay @ Nom-Sup:150 ns传播延迟(tpd):150 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

MM74C907N 数据手册

 浏览型号MM74C907N的Datasheet PDF文件第2页浏览型号MM74C907N的Datasheet PDF文件第3页浏览型号MM74C907N的Datasheet PDF文件第4页浏览型号MM74C907N的Datasheet PDF文件第5页 
October 1987  
Revised January 1999  
MM74C906 • MM74C907  
Hex Open Drain N-Channel Buffers •  
Hex Open Drain P-Channel Buffers  
All inputs are protected from static discharge by diode  
clamps to VCC and to ground.  
General Description  
The MM74C906 and MM74C907 buffers employ monolithic  
CMOS technology in achieving open drain outputs. The  
MM74C906 consists of six inverters driving six N-channel  
devices; and the MM74C907 consists of six inverters driv-  
ing six P-channel devices. The open drain feature of these  
buffers makes level shifting or wire AND and wire OR func-  
tions by just the addition of pull-up or pull-down resistors.  
Features  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1V  
High noise immunity: 0.45 VCC (typ.)  
High current sourcing and sinking open drain outputs  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74C906M  
MM74C906N  
MM74C907N  
M14A  
N14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagrams  
Pin Assignments for DIP and SOIC  
MM74C906  
MM74C907  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005911.prf  
www.fairchildsemi.com  

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