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MM74C02 PDF预览

MM74C02

更新时间: 2024-11-24 22:30:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
6页 81K
描述
Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverter

MM74C02 数据手册

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October 1987  
Revised January 1999  
MM74C00 • MM74C02 • MM74C04  
Quad 2-Input NAND Gate •  
Quad 2-Input NOR Gate •  
Hex Inverter  
All inputs are protected from damage due to static dis-  
charge by diode clamps to VCC and GND.  
General Description  
The MM74C00, MM74C02, and MM74C04 logic gates  
employ complementary MOS (CMOS) to achieve wide  
power supply operating range, low power consumption,  
high noise immunity and symmetric controlled rise and fall  
times. With features such as this the 74C logic family is  
close to ideal for use in digital systems. Function and pin  
out compatibility with series 74 devices minimizes design  
time for those designers already familiar with the standard  
74 logic family.  
Features  
Wide supply voltage range: 3V to 15V  
Guaranteed noise margin: 1V  
High noise immunity: 0.45 VCC (typ.)  
Low power consumption: 10 nW/package (typ.)  
Low power: TTL compatibility:  
Fan out of 2 driving 74L  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74C00M  
MM74C00N  
MM74C02N  
MM74C04M  
MM74C04N  
M14A  
N14A  
M14A  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagrams  
Pin Assignments for DIP and SOIC  
MM74C00  
MM74C02  
Top View  
Top View  
MM74C04  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005877.prf  
www.fairchildsemi.com  

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