MM54HC237

更新时间： 2024-11-25 10:53:11

品牌	Logo	应用领域
美国国家半导体 - NSC		解码器锁存器
页数	文件大小	规格书
6页	147K
描述
3-to-8 Line Decoder With Address Latches

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MM54HC237 数据手册

January 1988

MM54HC237/MM74HC237

3-to-8 Line Decoder With Address Latches

General Description

These devices utilize advanced silicon-gate CMOS technol-

ogy, to implement a three-to-eight line decoder with latches

on the three address inputs. When GL goes from low to

high, the address present at the select inputs (A, B and C) is

stored in the latches. As long as GL remains high no ad-

dress changes will be recognized. Output enable controls,

G1 and G2, control the state of the outputs independently of

the select or latch-enable inputs. All of the outputs are low

unless G1 is high and G2 is low. The ’HC237 is ideally suit-

ed for the implementation of glitch-free decoders in stored-

address applications in bus oriented systems.

The 54HC/74HC logic family is speed, function and pin-out

compatible with the standard 54LS/74LS logic family. All

inputs are protected from damage due to static discharge by

diodes to V

and ground.

Features

Typical propagation delay: 20 ns

Wide supply range: 2–6V

Latched inputs for easy interfacing

Fanout of 10 LS-TTL loads

Connection Diagram

Dual-In-Line Package

TL/F/5326–1

Top View

Order Number MM54HC237 or MM74HC237

Truth Table

INPUTS

OUTPUTS

ENABLE

GL G1 G2

SELECT

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Output corresponding to stored

address, L; all others, H

low level, X irrelevant

high level, L

1995 National Semiconductor Corporation

TL/F/5326

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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