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ML145146RP PDF预览

ML145146RP

更新时间: 2024-11-07 04:15:27
品牌 Logo 应用领域
LANSDALE 光电二极管输入元件
页数 文件大小 规格书
12页 3648K
描述
4-Bit Data Bus Input PLL Frequency Synthesizer

ML145146RP 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:7-BIT AUXILIARY INPUT COUNTER模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZER
JESD-30 代码:R-PDIP-T20长度:26.415 mm
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):9 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

ML145146RP 数据手册

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ML145146  
4–Bit Data Bus Input PLL  
Frequency Synthesizer  
INTERFACES WITH DUAL–MODULUS PRESCALERS  
Legacy Device: Motorola MC145146-2  
The ML145146 is programmed by a 4–bit input, with  
strobe and address lines. The device features consist of a  
reference oscillator, 12–bit programmable reference  
divider, digital phase detector, 10–bit programmable  
divide–by–N counter, 7–bit divide–by–A counter, and the  
necessary latch circuitry for accepting the 4–bit input data.  
P DIP 20 = RP  
PLASTIC DIP  
CASE 738  
20  
1
SOG 20 W = -6P  
SOG PACKAGE  
CASE 751D  
20  
• Operating Temperature Range: T – 40 to +85°C  
A
• Low Power Consumption Through the Use of  
CMOS Technology  
• 3.0 to 9.0 V Supply Range  
• Programmable Reference Divider for Values Between  
3 and 4095  
• Dual–Modulus 4–Bit Data Bus Programming  
• ÷ N Range = 3 to 1023, ÷ A Range= 0 to 127  
• “Linearized” Digital Phase Detector Enhances  
Transfer Function Linearity  
1
CROSS REFERENCE/ORDERING INFORMATION  
PACKAGE  
MOTOROLA  
LANSDALE  
P DIP 20  
SOG 20W  
MC145146P2  
ML145146RP  
MC145146DW2 ML145146-6P  
Note: Lansdale lead free (Pb) product, as it  
becomes available, will be identified by a part  
number prefix change from ML to MLE.  
Two Error Signal Options:  
PIN ASSIGNMENT  
Single–Ended (Three–State)  
Double–Ended  
D1  
D0  
1
2
20  
19  
D2  
D3  
f
3
4
18  
17  
f
R
in  
V
φ
R
SS  
BLOCK DIAGRAM  
PD  
V
5
6
16  
15  
φ
V
out  
f
DD  
V
f
12–BIT  
L5  
÷R COUNTER  
OSC  
in  
R
OSC  
in  
7
14  
13  
12  
11  
MC  
LD  
ST  
A2  
OSC  
out  
OSC  
8
out  
L6  
L7  
LOCK  
DETECT  
LD  
PD  
A0  
9
D0  
D1  
D2  
D3  
A2  
A1  
A0  
A1  
10  
PHASE  
DETECTOR A  
out  
LATCH  
CONTROL  
CIRCUITRY  
LATCHES  
f
V
ST  
φ
V
PHASE  
L2  
L3  
L4  
L0  
L1  
DETECTOR B  
φ
R
f
in  
10–BIT  
÷
N COUNTER  
7–BIT  
÷
A COUNTER  
MODULUS CONTROL (MC)  
CONTROL LOGIC  
Page 1 of 12  
www.lansdale.com  
Issue 0  

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