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MK3235-01SLF PDF预览

MK3235-01SLF

更新时间: 2024-11-10 14:53:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 67K
描述
Clock Generator, 14.3MHz, PDSO16, SOIC-16

MK3235-01SLF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:NJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:14.3 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:0.032768 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK3235-01SLF 数据手册

 浏览型号MK3235-01SLF的Datasheet PDF文件第2页浏览型号MK3235-01SLF的Datasheet PDF文件第3页浏览型号MK3235-01SLF的Datasheet PDF文件第4页 
MK3235  
Handheld System Clock Synthesizer  
ICR O CLOC K  
Description  
Features  
• Input crystal frequency of 32.768 kHz  
• Lowest power solution available  
The MK3235 is the smallest size, lowest power system  
clock synthesizer available. It is the ideal way to  
generate clocks for handheld computers, such as PDAs,  
PICs, and other devices where low power is required.  
Using analog Phase-Locked Loop (PLL) techniques,  
the device operates from a single 32.768 kHz crystal to  
produce the 32.768kHz, 14.318MHz, and serial  
communications output clocks.  
• Lowest profile clock solution where height is critical  
• Three output clocks  
• 3.3V or 5.0V operation  
• Duty cycle of 45/55  
The device has three power down modes for the  
14.3MHz, communications, and 32.768kHz clocks.  
• 14.3MHz or 14.3MHz+Comm clock power downs  
• Separate battery supply pin for 32 kHz runs to 2V  
• IDD less than 4µA when 32 kHz running  
• Packaged in 16 pin narrow SOIC  
The MK3235 can save board space and cost even if it  
only replaces the 32kHz oscillator circuitry and one  
additional surface mount crystal or oscillator. The  
extremely low IDD, the ease of surface mounting, and  
the power down capability are added benefits in using  
the part.  
Block Diagram  
VDD GND  
14.318MHz  
PD14  
Output  
Buffer  
Clock Synthesis  
and Control  
Circuitry  
14.3 MHz  
PDCOMM  
PD  
Communications  
Clock Synthesis  
and Control  
Output  
Buffer  
1.843 or  
3.686 MHz  
VDD32  
Circuitry  
32.768 kHz  
crystal  
X1  
Crystal  
Oscillator  
Output  
Buffer  
32.768 kHz  
X2  
MDS 3235 D  
1
Revision 092397  
Printed 11/16/00  
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com  

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