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MK3230-01SLF PDF预览

MK3230-01SLF

更新时间: 2024-11-24 19:27:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 61K
描述
Clock Generator, 80MHz, PDSO16, 0.150 INCH, SOIC-16

MK3230-01SLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G16长度:9.9 mm
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:80 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED主时钟/晶体标称频率:0.032768 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

MK3230-01SLF 数据手册

 浏览型号MK3230-01SLF的Datasheet PDF文件第2页浏览型号MK3230-01SLF的Datasheet PDF文件第3页浏览型号MK3230-01SLF的Datasheet PDF文件第4页 
MK3230  
Portable System Clock Synthesizer  
Features  
Description  
The MK3230 is the smallest size, lowest power  
system clock synthesizer available. It is the ideal way  
to generate clocks for portable computers, PDAs,  
and other devices where low power is required.  
Using analog Phase-Locked Loop (PLL)  
techniques, the device operates from a single  
32.768 kHz crystal to produce the 32.768kHz, CPU,  
system, keyboard controller, and floppy (or super  
I/O) controller output clocks.  
• Packaged in 16 pin narrow (0.150”) SOIC  
• Input crystal frequency of 32.768 kHz  
• Lowest power solution available  
• Lowest profile clock solution where height is critical  
• Output clock frequencies up to 80 MHz  
• Five output clocks  
• 3.3V or 5.0V operation  
• Duty cycle of 45/55  
• Seven selectable CPU frequencies  
• CPU and peripheral clock power downs  
• Separate battery supply pin for 32 kHz  
• IDD less than 5µA when 32 kHz running  
• 12MHz keyboard clock output  
• 14.3MHz output is not suitable for driving PLL for  
CRT. Will drive all other functions  
• 32kHz crystals require long startup (>500ms)  
The device has two power down modes. From the  
CPU decoding table (when FS0, FS1, and FS2 all  
are low), the CPU and 14.3 MHz system clocks can  
be turned off. Also, the keyboard and 24 MHz  
peripheral clocks can be shut off from PD24+KBD  
(pin 10). The part has a separate VDD32 pin for the  
32 kHz clock, allowing it to run at a different voltage  
(down to 2.0V) from the rest of the chip, allowing it  
to run from a back-up battery.  
Block Diagram  
VDD  
GND  
Output  
CPUS0  
CPUS1  
CPUS2  
CPUCLK  
Buffer  
Output  
12 MHz  
Buffer  
Clock Synthesis  
and Control Circuitry  
Output  
Buffer  
PD24+KBD  
24.00 MHz  
14.32 MHz  
Output  
Buffer  
VDD32  
X1  
Crystal  
Oscillator  
Output  
Buffer  
32.768 kHz  
X2  
32.768 kHz  
crystal  
MDS 3230 G  
1
Revision 100901  
Integrated Circuit Systems, Inc.• 525 Race Street•San Jose • CA • 95126 • (408)295-9800tel • www.icst.com  

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