Datasheet > MK2771-16R

MK2771-16R

更新时间： 2024-11-20 22:46:15

品牌	Logo	应用领域
矽成 - ICSI		石英晶振压控振荡器时钟
页数	文件大小	规格书
4页	70K
描述
VCXO and Set-Top Clock Source

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数据手册

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MK2771-16R 数据手册

MK2771-16

VCXO and Set-Top Clock Source

_{ICR O}C_{LOC K}

Description

Features

The MK2771-16 is a low cost, low jitter, high

performance VCXO and clock synthesizer

designed for set-top boxes. The on-chip Voltage

Controlled Crystal Oscillator accepts a 0 to 3V

input voltage to cause the output clocks to vary by

±100 ppm. Using ICS/MicroClock’s patented

VCXO and analog Phase-Locked Loop (PLL)

techniques, the device uses an inexpensive

13.5 MHz crystal input to produce multiple

output clocks including a selectable processor

clock, a selectable audio clock, two

communications clocks, a 13.5 MHz clock, and

three 27 MHz clocks. All clocks are frequency

locked to the 27.00MHz output (and to each

other) with zero ppm error, so any output can be

used as the VCXO output.

• Packaged in 28 pin SSOP (QSOP)

• On-chip patented VCXO with pull range

of 200ppm (minimum)

• VCXO tuning voltage of 0 to 3V

• Processor frequency include 16.66, 20, 25, 32, 40,

and 50 MHz

• Audio clocks support 32 kHz, 44.1 kHz, 48 kHz

and 96 kHz sampling rates

• Zero ppm synthesis error in all clocks (all exactly

track 27MHz VCXO)

• Uses an inexpensive 13.5 MHz crystal

• Full CMOS output swings with 25mA output

drive capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• 5V operating voltage with 3.3V capable I/O

VDD5

VDDIO

GND

Block Diagram

Output

Buffer

ACLK

PCLK

AS2:0

Output

Buffer

PS1, PS0

PLL

Clock

Synthesis

Circuitry

CS1, CS0

Output

Buffer

CCLK1

CCLK2

VIN

Output

Buffer

Voltage

Controlled

Crystal

13.5 MHz

pullable

crystal

Output

Buffers

PLL

27.000 MHz

13.500 MHz

Oscillator

Output

Buffer

÷2

MDS 2771-16 C

Revision 102099

Printed 11/16/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com

12 3 4

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