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MK2731-04STRLF PDF预览

MK2731-04STRLF

更新时间: 2024-11-21 20:10:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 59K
描述
Video Clock Generator, 36.864MHz, CMOS, PDSO16, 0.150 INCH, SOIC-16

MK2731-04STRLF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:36.864 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED主时钟/晶体标称频率:14.4 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEOBase Number Matches:1

MK2731-04STRLF 数据手册

 浏览型号MK2731-04STRLF的Datasheet PDF文件第2页浏览型号MK2731-04STRLF的Datasheet PDF文件第3页浏览型号MK2731-04STRLF的Datasheet PDF文件第4页 
PRELIMINARY INFORMATION  
MK2731-04C  
MPEG Audio Clock  
Features  
Description  
The MK2731-04 is a low cost, low jitter, high  
performance clock synthesizer designed to replace  
expensive discrete clock oscillators in MPEG audio  
applications. Using ICS/MicroClock’s patented  
analog/digital Phase-Locked Loop (PLL)  
techniques, the device uses an inexpensive  
14.4 MHz crystal input to produce all of the  
popular audio sampling frequencies.  
• Packaged in 16 pin narrow SOIC  
• Replaces multiple oscillators  
• 3.3V or 5V operation  
• Uses an inexpensive 14.4 MHz crystal  
• Supports 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz  
audio sampling rates  
Has 256x, 384x, and 512x sampling rates -  
compatible with every popular audio DAC  
• Zero ppm synthesis error  
ICS manufactures the largest variety of Set-Top  
Box and multimedia clock synthesizers for all  
applications. Consult ICS to eliminate VCXOs,  
crystals and oscillators from your board.  
• 25 mA output drive capability at TTL levels  
• Advanced, low power, sub-micron CMOS process  
Block Diagram  
VDD  
3
GND  
3
3
S2:S0  
Output  
CLK2  
Buffer  
PLL/Clock  
Synthesis  
Circuitry  
X1  
14.40 MHz  
Crystal  
Oscillator  
Output  
Buffer  
crystal  
÷ 2  
CLK1  
X2  
MDS 2731-04 CA  
1
Revision 122799  
Printed 11/16/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com  

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