Datasheet > MK2049-45SILFTR

MK2049-45SILFTR

更新时间： 2024-11-24 21:55:11

品牌	Logo	应用领域
矽成 - ICSI		通信时钟
页数	文件大小	规格书
9页	184K
描述
3.3V Communications Clock PLL

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MK2049-45SILFTR 数据手册

MK2049-45

3.3V Communications Clock PLL

Description

Features

The MK2049-45 is a dual Phase-Locked Loop (PLL)

device which can provide frequency synthesis and jitter

attenuation. The first PLL is VCXO based and uses a

pullable crystal to track signal wander and attenuate

input jitter. The second PLL is a translator for frequency

multiplication. Basic configuration is determined by a

Mode/Frequency Selection Table. Loop bandwidth and

damping factor are programmable via external loop

filter component selection.

• Packaged in 20 pin SOIC

• 3.3 V + 5% operation

• Meets the TR62411, ETS300 011, and GR-1244

specification for MTIE, Pull-in/Hold-in Range, Phase

Transients, and Jitter Generation for Stratum 3, 4,

and 4E

• Accepts multiple inputs: 8 kHz backplane clock, or 10

to 50 MHz

• Locks to 8 kHz + 100 ppm (External mode)

• Buffer Mode allows jitter attenuation of 10 - 50 MHz

Buffer Mode accepts a 10 to 50MHz input and will

provide a jitter attenuated output at 0.5 x ICLK, 1 x

ICLK or 2 x ICLK. In this mode the MK2049-45 is ideal

for filtering jitter from high frequency clocks.

input and x1 / x0.5 or x1 / x2 outputs

• Exact internal ratios enable zero ppm error

• Output rates include T1, E1, T3, E3, and OC3

submultiples

In External Mode, ICLK accepts an 8 kHz clock and will

produce output frequencies from a table of common

communciations clock rates, CLK and CLK/2. This

allows for the generation of clocks frequency-locked to

an 8 kHz backplane clock, simplifying clock

• Available in Pb (lead) free package

• See also the MK2049-34 and MK2049-36

synchronization in communications systems.

The MK2049-45 can be dynamically switched between

T1, E1, T3, E3 outputs with the same 24.576 MHz

crystal.

ICS can customize these devices for many other

different frequencies. Contact your ICS representative

for more details.

Block Diagram

C_S

C_L

C_LOptional Crystal Load Caps

R_SET

C_P

R_S

External Pullable Crystal

ISET

CAP2

CAP1 X1

Phase

Detector

Reference

Divider

Reference

Divider

Output

Divider

ICLK

VCXO

VCO

CLK

(used in buffer

mode only)

Charge

Pump

Divide

by 2

CLK/2

Feedback

Divider

Feedback

Divider (N)

Translator

PLL

VCXO

PLL

Divider Value

Look-up Table

FS3:0

MDS 2049-45 G

Revision 101904

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7...9

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与MK2049-45SILFTR相关器件

型号	品牌	获取价格	描述	数据表
MK2049-45SITR	ICSI	获取价格	3.3V Communications Clock PLL
MK2050FE-R52	OHMITE	获取价格	RES 205 OHM 1/4W 1% AXIAL
MK2058-01	ICSI	获取价格	Communications Clock Jitter Attenuator
MK2058-01SI	ICSI	获取价格	Communications Clock Jitter Attenuator
MK2058-01SITR	ICSI	获取价格	Communications Clock Jitter Attenuator
MK2059-01	ICSI	获取价格	VCXO-Based Frame Clock Frequency Translator
MK2059-01SI	ICSI	获取价格	VCXO-Based Frame Clock Frequency Translator
MK2059-01SITR	ICSI	获取价格	VCXO-Based Frame Clock Frequency Translator
MK2069-01	ICSI	获取价格	VCXO-Based Line Card Clock Synchronizer
MK2069-01GI	ICSI	获取价格	VCXO-Based Line Card Clock Synchronizer

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