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MK2049-01SITR PDF预览

MK2049-01SITR

更新时间: 2024-11-24 22:15:35
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路光电二极管通信时钟
页数 文件大小 规格书
11页 139K
描述
Communications Clock PLL

MK2049-01SITR 数据手册

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MK2049-01  
Communications Clock PLL  
Description  
Features  
• Packaged in 20 pin SOIC  
The MK2049 is a Phase-Locked Loop (PLL) based  
clock synthesizer, which accepts an 8 kHz clock  
input as a reference and generates T1, E1, T3, E3,  
and OC3 frequencies. The device can also accept a  
T1, E1, T3, or E3 input clock and provide the  
same output for loop timing. All outputs are  
frequency locked together and to the input. This  
allows for the generation of locked clocks to an  
8 kHz backplane clock, simplifying clock  
• Meets the TR62411, ETS300 011, and GR-1244  
specification for MTIE, Pull-in/Hold-in Range,  
Phase Transients, and Jitter Generation for  
Stratum 3, 4, and 4E  
• Accepts multiple inputs: 8 kHz backplane clock or  
Loop Timing frequencies  
distribution in communications systems.  
• Locks to 8 kHz ±100 ppm (External mode)  
• Exact internal ratios eliminate the need for external  
dividers  
MicroClock can customize this device for many  
other different frequencies. Contact your  
MicroClock representative for more details.  
• Zero ppm synthesis error in all output clocks.  
• Output clock rates include T1, E1, T3, E3, and  
OC3÷8  
For a fixed input-output phase relationship, refer  
to the MK2049-02, -03, or -3x. The MK2049-3x  
are 3.3 V devices.  
• 5 V ±5% operation  
• Offered in Commercial and Industrial temperature  
versions  
Block Diagram  
VDD GND  
4
4
4
FS3:0  
Output  
Buffer  
PLL  
Clock  
Synthesis,  
Control, and  
Jitter  
Attenuation  
Circuitry  
CLK1  
CLK2  
8 kHz  
External/  
Loop  
Timing  
Mux  
Clock  
Input  
Output  
Buffer  
Reference  
Crystal  
Output  
Buffer  
X1  
X2  
Crystal  
Oscillator  
CAP1  
CAP2  
MDS 2049-01 J  
1
Revision 040601  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com  

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