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MK1417SLF PDF预览

MK1417SLF

更新时间: 2024-11-27 20:06:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
4页 29K
描述
Processor Specific Clock Generator, 27MHz, CMOS, PDSO8, SOIC-8

MK1417SLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:27 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

MK1417SLF 数据手册

 浏览型号MK1417SLF的Datasheet PDF文件第2页浏览型号MK1417SLF的Datasheet PDF文件第3页浏览型号MK1417SLF的Datasheet PDF文件第4页 
PRELIMIN ARY IN FO RMAT IO N  
PRELIMIN ARY IN FO RMAT IO N  
MK1417  
S3 Notebook Clock Source  
Description  
Features  
• Packaged in 8 pin SOIC  
The MK1417 is an ideal way to generate clocks for  
S3’s M5 processor. The chip is a cost reduction to  
the MK1416, maintaining the functionality of the  
MK1416, but with a different pinout. In an 8 pin  
SOIC, the chip saves cost over separate surface  
mount oscillators and increases reliability by  
eliminating mechanical (quartz-based) devices  
from the board. The power down pin turns off the  
device, drawing less than 30µA.  
• Functional, lower cost replacement of MK1416  
• Differences from MK1416  
- no on-chip crystal capacitors  
- pinout is different  
• Ideal for S3’s M5 processor  
• Input clock frequency of 14.31818 MHz  
• Dual buffered 14.318 MHz clock outputs  
• Output clock frequency of 27.0MHz  
• Power down turns off chip  
MicroClock offers many other clocks for  
computers and computer peripherals. Consult  
MicroClock when you need to remove crystals and  
oscillators from your board.  
• Low jitter  
• 25mA drive capability at TTL levels  
• 3.3V or 5V supply voltage  
• Advanced, low power CMOS process  
• Insensitive to input clock duty cycle  
Block Diagram  
VDD GND  
Output  
27.000 MHz  
Buffer  
PD  
PLL  
Clock Synthesis  
and Control  
Circuitry  
14.31818 MHz  
Output  
Buffer  
14.31818 MHz  
14.31818 MHz  
crystal or clock  
X1/ICLK  
Crystal  
Oscillator  
Output  
Buffer  
X2  
(Capacitors are required for tuning)  
MDS1417B  
1
Revision 12157  
Printed 12/16/97  
MicroClock division of ICS•1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax  

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