Document Number: IMXRT1024CEC
Rev. 2, 01/2022
NXP Semiconductors
Data Sheet: Technical Data
MIMXRT1024DAG5A
MIMXRT1024DAG5B
i.MX RT1024 Crossover
Processors Data Sheet
for Consumer Products
Package Information
Plastic Package
144-Pin LQFP, 20 x 20 mm, 0.5 mm pitch
Ordering Information
See Table 2 on page 6
1 i.MX RT1024 introduction
The i.MX RT1024 is a processor of i.MX RT family
featuring NXP’s advanced implementation of the Arm
1. i.MX RT1024 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
1.3. Package marking information . . . . . . . . . . . . . . . . 8
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1. Special signal considerations . . . . . . . . . . . . . . . 16
3.2. Recommended connections for unused analog
®
®
Cortex -M7 core, which operates at speeds up to 500
MHz to provide high CPU performance and real-time
response.
The i.MX RT1024 processor has 4 MB on-chip flash.
256 KB on-chip RAM can be flexibly configured as
TCM or general-purpose on-chip RAM. The i.MX
RT1024 integrates advanced power management module
with DCDC and LDO that reduces complexity of
external power supply and simplifies power sequencing.
The i.MX RT1024 also provides various memory
interfaces, including SDRAM, RAW NAND FLASH,
NOR FLASH, SD/eMMC, Quad SPI, and a wide range
of connectivity interfaces including UART, SPI, I2C,
USB, and CAN; for connecting peripherals including
WLAN, Bluetooth™, and GPS. The i.MX RT1024 also
has rich audio features, including SPDIF and I2S audio
interface. Various analog IP integration, including ADC,
analog comparator, temperature sensor, etc.
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 18
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 24
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5. External memory interface . . . . . . . . . . . . . . . . . 40
4.6. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.7. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.8. Communication interfaces . . . . . . . . . . . . . . . . . . 60
4.9. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5. Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1. Boot mode configuration pins . . . . . . . . . . . . . . . 75
6.2. Boot device interface allocation . . . . . . . . . . . . . . 75
7. Package information and contact assignments . . . . . . . 80
7.1. 20 x 20 mm package information . . . . . . . . . . . . 80
8. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Legal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
© 2020-2022 NXP B.V.
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