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A1425A-PLG84I PDF预览

A1425A-PLG84I

更新时间: 2024-01-20 06:21:20
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟现场可编程门阵列可编程逻辑
页数 文件大小 规格书
90页 4491K
描述
Field Programmable Gate Array, 310 CLBs, 2500 Gates, 125MHz, CMOS, PQCC84, ROHS COMPLIANT, PLASTIC, LCC-84

A1425A-PLG84I 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:PLASTIC, LCC-84Reach Compliance Code:compliant
风险等级:5.77其他特性:MAX 70 I/OS
最大时钟频率:116.8 MHzCLB-Max的组合延迟:3 ns
JESD-30 代码:S-PQCC-J84JESD-609代码:e3
长度:29.3116 mm湿度敏感等级:3
可配置逻辑块数量:310等效关口数量:2500
输入次数:70逻辑单元数量:310
输出次数:70端子数量:84
最高工作温度:85 °C最低工作温度:-40 °C
组织:310 CLBS, 2500 GATES封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:29.3116 mm
Base Number Matches:1

A1425A-PLG84I 数据手册

 浏览型号A1425A-PLG84I的Datasheet PDF文件第2页浏览型号A1425A-PLG84I的Datasheet PDF文件第3页浏览型号A1425A-PLG84I的Datasheet PDF文件第4页浏览型号A1425A-PLG84I的Datasheet PDF文件第5页浏览型号A1425A-PLG84I的Datasheet PDF文件第6页浏览型号A1425A-PLG84I的Datasheet PDF文件第7页 
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
• More than 500 Macro Functions  
Features  
• Replaces up to Twenty 32 Macro-Cell CPLDs  
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000  
equivalent PLD Gates)  
• Replaces up to One Hundred 20-Pin PAL® Packages  
• Up to 1,153 Dedicated Flip-Flops  
• VQFP, TQFP, BGA, and PQFP Packages  
• Nonvolatile, User Programmable  
• Fully Tested Prior to Shipment  
• 5.0 V and 3.3 V Versions  
• Optimized for Logic Synthesis Methodologies  
• Low Power CMOS Technology  
• Highly Predictable Performance with 100% Automatic Place-  
and-Route  
• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)  
• Up to 186 MHz On-Chip Performance (–1 Speed Grade)  
• Up to 228 User-Programmable I/O Pins  
• Four Fast, Low-Skew Clock Networks  
Table 1 • ACT 3 Family Product Information  
Device  
A1415  
A1425  
A1440  
A1460  
A14100  
Capacity  
Gate Array Equivalent Gates  
1,500  
3,750  
40  
2,500  
6,250  
60  
4,000  
10,000  
100  
6,000  
15,000  
150  
10,000  
25,000  
250  
PLD Equivalent Gates  
TTL Equivalent Package (40 gates)  
20-Pin PAL Equivalent Packages (100 gates)  
Logic Modules  
15  
25  
40  
60  
100  
200  
104  
96  
310  
160  
150  
360  
100  
564  
848  
1,377  
697  
S-Module  
288  
432  
C-Module  
Dedicated Flip-Flops1  
276  
416  
680  
264  
568  
768  
1,153  
228  
User I/Os (maximum)  
80  
140  
168  
Maximum Performance2 (worst-case commercial, –1 speed grade)  
Chip-to-Chip3 (MHz)  
80  
47  
80  
47  
80  
47  
78  
47  
76  
47  
Accumulators (16-bit, MHz)  
Loadable Counter (16-bit, MHz)  
Prescaled Loadable Counters (16-bit, MHz)  
Datapath, Shift Registers (MHz)  
Clock-to-Output (pad-to-pad, ns)  
Packages4 (by pin count)  
82  
82  
82  
82  
78  
186  
186  
9.0  
186  
186  
9.0  
186  
186  
9.5  
150  
150  
10.0  
150  
150  
10.5  
CPGA  
PLCC  
PQFP  
RQFP  
VQFP  
TQFP  
BGA  
PG1005  
PL84  
PQ100  
PG1335  
PL84  
PQ100, PQ160  
PG1755  
PL84  
PQ160  
VQ100  
TQ176  
PG207  
PG257  
PQ160, PQ208  
VQ100  
RQ208  
VQ100  
TQ176  
BG2255  
CQ196  
BG313  
CQ256  
CQFP  
CQ132  
Notes:  
1. One flip-flop per S0Module, two flip-flops per I/O Module.  
2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.  
3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and  
Table 1-1 on page 1-2.  
4. See the "Product Plan" table on page III for package availability.  
5. Discontinued device and package combination.  
6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product  
Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:  
PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004  
January 2012  
I
© 2012 Microsemi Corporation  

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