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37LV128-IL PDF预览

37LV128-IL

更新时间: 2024-01-01 04:56:47
品牌 Logo 应用领域
美国微芯 - MICROCHIP 存储内存集成电路可编程只读存储器OTP只读存储器电动程控只读存储器时钟
页数 文件大小 规格书
12页 92K
描述
36K, 64K, and 128K Serial EPROM Family

37LV128-IL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.91最大时钟频率 (fCLK):10 MHz
I/O 类型:COMMONJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
内存密度:131072 bit内存集成电路类型:OTP ROM
内存宽度:32功能数量:1
端子数量:8字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX32输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm最大待机电流:0.00005 A
子类别:Other Memory ICs最大压摆率:0.01 mA
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.6 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

37LV128-IL 数据手册

 浏览型号37LV128-IL的Datasheet PDF文件第2页浏览型号37LV128-IL的Datasheet PDF文件第3页浏览型号37LV128-IL的Datasheet PDF文件第4页浏览型号37LV128-IL的Datasheet PDF文件第5页浏览型号37LV128-IL的Datasheet PDF文件第6页浏览型号37LV128-IL的Datasheet PDF文件第7页 
37LV36/65/128  
36K, 64K, and 128K Serial EPROM Family  
FEATURES  
PACKAGE TYPES  
• Operationally equivalent to Xilinx XC1700 family  
• Wide voltage range 3.0 V to 6.0 V  
PDIP  
DATA  
CLK  
1
2
3
4
8
7
6
5
VCC  
VPP  
CEO  
VSS  
• Maximum read current 10 mA at 5.0 V  
• Standby current 100 µA typical  
• Industry standard Synchronous Serial Interface/  
1 bit per rising edge of clock  
RESET/OE  
CE  
• Full Static Operation  
• Sequential Read/Program  
• Cascadable Output Enable  
SOIC  
• 10 MHz Maximum Clock Rate @ 5.0 Vdc  
• Programmable Polarity on Hardware Reset  
1
2
3
4
8
7
6
5
• Programming with industry standard EPROM pro-  
grammers  
VCC  
DATA  
CLK  
VPP  
CEO  
VSS  
• Electrostatic discharge protection > 4,000 volts  
• 8-pin PDIP/SOIC and 20-pin PLCC packages  
• Data Retention > 200 years  
RESET/OE  
CE  
Temperature ranges:  
-
Commercial: 0°C to +70°C  
- Industrial: -40°C to +85°C  
PLCC  
DATA VCC  
DESCRIPTION  
The Microchip Technology Inc. 37LV36/65/128 is a  
family of Serial OTP EPROM devices organized inter-  
nally in a x32 configuration. The family also features a  
cascadable option for increased memory storage  
where needed. The 37LV36/65/128 is suitable for  
many applications in which look-up table information  
storage is desirable and provides full static operation in  
the 3.0V to 6.0V VCC range. The devices also support  
the industry standard serial interface to the popular  
RAM-based Field Programmable Gate Arrays (FPGA).  
Advanced CMOS technology makes this an ideal boot-  
strap solution for today's high speed SRAM-based  
FPGAs. The 37LV36/65/128 family is available in the  
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin  
PLCC packages.  
4
5
6
7
8
CLK  
18  
17  
16  
15  
14  
VPP  
RESET/OE  
CE  
CEO  
Vss  
BLOCK DIAGRAM  
CE  
CEO  
RESET/OE  
Device  
Bits  
Programming Word  
OE  
37LV36  
37LV65  
37LV128  
36,288  
65,536  
131,072  
1134 x 32  
2048 x 32  
4096 x 32  
ADDRESS  
Counter  
EPROM  
ARRAY  
DATA  
CLK  
Xilinx is a registered trademark of Xilinx Corporation.  
1996 Microchip Technology Inc.  
DS21109E-page 1  
This document was created with FrameMaker 4 0 4  

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