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MDU28C-50 PDF预览

MDU28C-50

更新时间: 2024-11-19 20:13:47
品牌 Logo 应用领域
DATADELAY 输出元件逻辑集成电路延迟线
页数 文件大小 规格书
4页 39K
描述
ACTIVE DELAY LINE, TRUE OUTPUT, DIP8, LOW PROFILE, DIP-8

MDU28C-50 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:compliant风险等级:5.15
其他特性:TESTED WITH NO LOAD CONDITIONS系列:HC/UH
输入频率最大值(fmax):6.66667 MHzJESD-30 代码:R-XDIP-T8
JESD-609代码:e3逻辑集成电路类型:ACTIVE DELAY LINE
功能数量:2抽头/阶步数:1
端子数量:8最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED可编程延迟线:NO
认证状态:Not Qualified座面最大高度:7.747 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总延迟标称(td):50 ns
宽度:7.62 mmBase Number Matches:1

MDU28C-50 数据手册

 浏览型号MDU28C-50的Datasheet PDF文件第2页浏览型号MDU28C-50的Datasheet PDF文件第3页浏览型号MDU28C-50的Datasheet PDF文件第4页 
MDU28C  
Ò
DUAL, HCMOS-INTERFACED  
FIXED DELAY LINE  
(SERIES MDU28C)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
VDD  
N/C  
O1  
N/C  
N/C  
N/C  
O2  
I1  
N/C  
N/C  
N/C  
I2  
N/C  
VDD  
8
I1  
N/C  
I2  
1
2
3
4
·
·
·
·
·
·
Two independent delay lines  
Fits standard 8-pin DIP socket  
Low profile  
O1  
7
N/C  
6
Auto-insertable  
8
GND  
O2  
5
GND  
Input & outputs fully CMOS interfaced & buffered  
10 T2L fan-out capability  
MDU28C-xx  
DIP  
Military SMD  
MDU28C-xxA1 Gull-Wing  
MDU28C-xxB1 J-Lead  
MDU28C-xxMD1  
MDU28C-xxMD4  
MDU28C-xxM Military DIP  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
I1-I2  
Signal Inputs  
The MDU28C-series device is a 2-in-1 digitally buffered delay line. The  
signal inputs (I1-I2) are reproduced at the outputs (O1-O2), shifted in time  
by an amount determined by the device dash number (See Table). The  
delay lines function completely independently of each other.  
O1-O2 Signal Outputs  
VDD +5 Volts  
GND Ground  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Number  
Delay Per  
Line (ns)  
10 ± 2.0  
12 ± 2.0  
16 ± 2.0  
20 ± 2.0  
25 ± 2.0  
30 ± 2.0  
35 ± 2.0  
40 ± 2.0  
45 ± 2.2  
50 ± 2.5  
60 ± 3.0  
75 ± 3.7  
100 ± 5.0  
·
·
·
·
Minimum input pulse width: 100% of total delay  
Output rise time: 8ns typical  
Supply voltage: 5VDC ± 5%  
Supply current: ICCL = 40ma typical  
ICCH = 45ma typical  
Operating temperature: 0° to 70° C  
Temp. coefficient of total delay: 300 PPM/°C  
MDU28C-10  
MDU28C-12  
MDU28C-16  
MDU28C-20  
MDU28C-25  
MDU28C-30  
MDU28C-35  
MDU28C-40  
MDU28C-45  
MDU28C-50  
MDU28C-60  
MDU28C-75  
MDU28C-100  
·
·
O1  
100%  
I1  
O2  
100%  
I2  
NOTE: Any dash number between 10 and 100  
not shown is also available.  
VDD  
GND  
Functional block diagram  
Ó1997 Data Delay Devices  
Doc #97040  
12/12/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1

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