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MCXN946VDFT PDF预览

MCXN946VDFT

更新时间: 2024-11-12 17:14:51
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
139页 2695K
描述
MCX N94x/54x Highly Integrated Multicore MCUs with On-Chip Accelerators, Intelligent Peripherals and...

MCXN946VDFT 数据手册

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MCXNx4x  
32-bit Arm Cortex-M33 @ 150 MHz (N94x and N54x)  
Rev. 4 — 01/2024  
Data Sheet: Technical Data  
MCXN54x  
MCXN94x  
32-bit Arm® Dual Cortex-M33 TrustZone® microcontroller for Industrial and  
Consumer IoT Applications with USB HS and FS, CAN FD, LP Flexcomm  
Interface, SDIO, 32-bit counter/timers, SCTimer/PWM, FlexPWM, 4x 16-bit  
2.0 Msamples/sec ADC, Comparator, Temperature Sensor, PKC, AES,  
PUF, SHA, CRC, RNG  
• Highly secure: TrustZone for Armv8-M, secure boot/update ROM, NXP's  
184VFBGA  
®
100HLQFP  
EdgeLock secure subsystem (ELS) S50 black-box secure enclave  
9 x 9 x 0.86 mm,  
0.5 mm  
with key storage and crypto algorithms protected from side-channel  
attacks as well as internal/external tamper events, flash encryption,  
external memory interface with on-the-fly PRINCE decryption, options  
for hardware Physically Unclonable Function (PUF) and Factory Root of  
Trust programming  
14 x 14 x 1.4 mm,  
0.5 mm  
NOTE  
All information  
on the HLQFP  
package is  
preliminary and  
pending  
• Industrial Strength: Industrial communication protocol support, 15-year  
longevity, high-resolution mixed signal analog, CAN-FD, BLDC/PMSM  
Motor Control support, integrated sensor interfaces (MIPI-I3C, I2C, SPI)  
qualification.  
• Power-efficient: < 70 μA/MHz active current, < 10 μA Power down mode  
with RTC enabled and 8 KB SRAM retention, < 2.5 μA Deep Power-  
down mode with RTC active and 8 KB SRAM  
Target Applications  
Advanced Security  
• ELS S50  
— AES-256, SHA-2, RNG  
• Industrial and Consumer IoT  
• Industrial Communications  
• Smart Metering  
— ECC-256 (ECDSA, ECDH)  
• PKC (Asymmetric Crypto accelerator)  
• SRAM PUF for RoT Key  
• Motor Control  
• Automation & Control  
• Sensors  
• PRINCE OTF Encrypt/Decrypt for internal and external  
Flash  
CPU Core Platform  
• Protected Flash Region (PFR)  
• DICE and UID and Debug authentication  
• 2x Code Watchdog  
• Primary CPU: Cortex-M33  
— TrustZone, MPU, FPU, SIMD, ETM, CTI  
• Secondary CPU: Cortex-M33 Barebone  
• DSP Accelerator (PowerQUAD, w CP intf)  
• SmartDMA  
• Tamper Detect  
— Eight tamper pins  
— Active and passive tamper pin detect  
— Voltage tamper detect  
• N1-16 Neural Processing Unit (NPU)  
• Coolflux BSP32  
• Secure Multilayer Bus Matrix  
Table continues on the next page...  
NXP reserves the right to change the detail specifications as may be required to  
permit improvements in the design of its products.  

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