MCM72FB8ML7.5

更新时间： 2024-11-18 22:31:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		脉冲
页数	文件大小	规格书
20页	256K
描述
256K x 72 Bit Burst RAM Multichip Module

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中文翻译

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技术参数
数据手册

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MCM72FB8ML7.5 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA209,11X19,50	针数：	209
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	7.5 ns	I/O 类型：	COMMON
JESD-30 代码：	S-PBGA-B209	JESD-609代码：	e0
长度：	25 mm	内存密度：	18874368 bit
内存集成电路类型：	CACHE SRAM MODULE	内存宽度：	72
功能数量：	1	端口数量：	1
端子数量：	209	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX72	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA209,11X19,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5,3.3 V	认证状态：	Not Qualified
座面最大高度：	2.9 mm	最大待机电流：	0.12 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	1.7 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	BICMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	25 mm	Base Number Matches：	1

MCM72FB8ML7.5 数据手册

Order this document

by MCM72FB8ML/D

SEMICONDUCTOR TECHNICAL DATA

MCM72FB8ML

MCM72PB8ML

Advance Information

256K x 72 Bit BurstRAM

Multichip Module

MULTICHIP MODULE

PBGA

The256Kx72multichipmoduleusesfour4MbitsynchronousfaststaticRAMs

designed to provide a burstable, high performance, secondary cache for the

PowerPC and other high performance microprocessors. It is organized as

256K words of 72 bits each. This device integrates input registers, an output reg-

ister (MCM72PB8ML only), a 2–bit address counter, and high speed SRAM onto

a single monolithic circuit for reduced parts count in cache data RAM applica-

tions. Synchronous design allows precise cycle control with the use of an exter-

nal clock (K). BiCMOS circuitry reduces the overall power consumption of the

integrated functions for greater reliability.

CASE 1103B–01

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally (burst sequence operates in linear or

interleaved mode dependent upon the state of LBO) and controlled by the burst

address advance (ADV) input pin.

PIN A1

INDICATION

(corner without

fiducial)

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The eight bytes are designated as “a” through “h”. SBa controls DQa,

SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx

are asserted with SW. All bytes are written if either SGW is asserted or if all SBx

and SW are asserted.

TOP VIEW

The module can be configured as either a pipelined or flow–through SRAM.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge–

triggered output register and then released to the output buffers at the next rising

edge of clock (K). Flow–through SRAMs allow output to simply flow freely from

the memory array.

The multichip module operates from a 3.3 V core power supply and all outputs

operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are

JEDEC standard JESD8–5 compatible.

•

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Option for Pipeline or Flow–Through (Speeds Guaranteed When Module is

Purchased by Appropriate Part Number)

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

JEDEC BGA Pin Assignment

PIN A1

INDICATION

BOTTOM VIEW

(corner with

fiducial)

(Drawings Not to Scale)

•

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

7/30/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM72FB8ML MCM72PB8ML

12 3 4 5 6 7...20

中文翻译

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与MCM72FB8ML7.5相关器件

型号	品牌	获取价格	描述	数据表
MCM72FB8ML7.5R	MOTOROLA	获取价格	256K x 72 Bit Burst RAM Multichip Module
MCM72FB8ML8	MOTOROLA	获取价格	256K x 72 Bit Burst RAM Multichip Module
MCM72FB8ML8R	MOTOROLA	获取价格	256K x 72 Bit Burst RAM Multichip Module
MCM72JG32	MOTOROLA	获取价格	256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium
MCM72JG32SG66	MOTOROLA	获取价格	256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium
MCM72JG64SG66	MOTOROLA	获取价格	256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium
MCM72MS32SG50	MOTOROLA	获取价格	32KX72 CACHE SRAM MODULE, 14ns, DMA136
MCM72MS32SG60	MOTOROLA	获取价格	32KX72 CACHE SRAM MODULE, 11ns, DMA136
MCM72MS32SG66	MOTOROLA	获取价格	32KX72 CACHE SRAM MODULE, 9ns, DMA136
MCM72MS64SG50	MOTOROLA	获取价格	64KX72 CACHE SRAM MODULE, 14ns, DMA136

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