Datasheet > MCM69T618ZP6

MCM69T618ZP6

更新时间： 2024-09-30 21:10:27

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		信息通信管理静态存储器
页数	文件大小	规格书
12页	373K
描述
Cache Tag SRAM, 64KX18, 6ns, BICMOS, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119

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MCM69T618ZP6 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM69T618

Product Preview

64K x 18 Bit Synchronous

Pipelined Cache Tag RAM

The MCM69T618 is a 1M bit synchronous fast static RAM with integrated tag

compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB

secondary cache as well as to be used as a data RAM for 512KB caches. This

device is organized as 64K words of 18 bits each, fabricated with Motorola’s high

performance silicon gate BiCMOS technology. It integrates input registers, out-

put registers, tag comparators, and high speed SRAM onto a single monolithic

circuit for reduced parts count in cache tag RAM applications. Synchronous

design allows precise cycle control with the use of an external clock (K). BiCMOS

circuitry reduces the overall power consumption of the integrated functions for

greater reliability.

ZP PACKAGE

PBGA

CASE 999–01

Addresses (SA), data inputs (DQ), write enable (SW) and chip enable (SE0

and SE1) are all controlled through positive–edge–triggered noninverting regis-

ters. Data enable (DE) is sampled on the rising clock edge while output enable

(G) and match output enable (MG) are asynchronous.

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

TQ PACKAGE

TQFP

CASE 983A–01

For read cycles, pipelined SRAM output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

Compare cycles begin as read cycles with output disabled so compare data

can be loaded into the input register. The comparator compares the read data

with the registered input data, and a match signal is generated. The match output

is also stored by an output register and released to the match output buffer at the

next rising edge of clock (K).

The MCM69T618 operates from a single 3.3 V power supply and all inputs and

outputs are LVTTL compatible.

•

MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle

MCM69T618–6 = 6 ns Clock–to–Match / 12 ns cycle

MCM69T618–7 = 7 ns Clock–to–Match / 13.3 ns cycle

Single 3.3 V +10%, –5% Power Supply

•

Pipelined Data Comparator

Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path

64K x 18 Organization Supports Up to 2MB Cache

Synchronous Data Input Register Load Enable (DE)

Internally Self–Timed Write Cycle

Asynchronous Data I/O Output Enable (G)

Asynchronous Match Output Enable (MG)

119 Bump, 50 mil (1.27 mm) Pitch, 7 x 17 Plastic Ball Grid Array (PBGA)

and 100 Pin TQFP Packages.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1

3/18/96

Motorola, Inc. 1996

MOTOROLA FAST SRAM

MCM69T618

12 3 4 5 6 7...12

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与MCM69T618ZP6相关器件

型号	品牌	获取价格	描述	数据表
MCM69T618ZP6R	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM6L4400BN50	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 50ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN50R2	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 50ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN60	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 60ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN60R2	MOTOROLA	获取价格	Fast Page DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN70	MOTOROLA	获取价格	Fast Page DRAM, 1MX4, 70ns, CMOS, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN70R2	MOTOROLA	获取价格	Fast Page DRAM, 1MX4, 70ns, CMOS, PDSO20, 0.300 INCH, SOJ-26/20
MCM72100SG80	MOTOROLA	获取价格	1MX72 FAST PAGE DRAM MODULE, 80ns, SMA100, SIMM-100
MCM72200SG60	MOTOROLA	获取价格	2M X 72 FAST PAGE DRAM MODULE, 60 ns, SMA100, SIMM-100
MCM72200SG70	MOTOROLA	获取价格	2M X 72 FAST PAGE DRAM MODULE, 70 ns, SMA100, SIMM-100

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