Datasheet > 存储 > SRAM> MCM69T618TQ5R

MCM69T618TQ5R

更新时间： 2024-09-29 22:20:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器信息通信管理
页数	文件大小	规格书
10页	182K
描述
64K x 18 Bit Synchronous Pipelined Cache Tag RAM

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技术参数
数据手册

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MCM69T618TQ5R 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.56
Is Samacsys：	N	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	1179648 bit
内存集成电路类型：	CACHE TAG SRAM	内存宽度：	18
功能数量：	1	端口数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	110 °C	最低工作温度：	20 °C
组织：	64KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

MCM69T618TQ5R 数据手册

Order this document

by MCM69T618/D

SEMICONDUCTOR TECHNICAL DATA

MCM69T618

64K x 18 Bit Synchronous

Pipelined Cache Tag RAM

The MCM69T618 is a 1M–bit synchronous fast static RAM with integrated tag

compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB

secondary cache as well as to be used as a data RAM for 512KB caches. This

device is organized as 64K words of 18 bits each. It integrates input registers,

output registers, tag comparators, and high speed SRAM onto a single mono-

lithic circuit for reduced parts count in cache tag RAM applications. Synchronous

design allows precise cycle control with the use of an external clock (K). BiCMOS

circuitry reduces the overall power consumption of the integrated functions for

greater reliability.

TQ PACKAGE

TQFP

CASE 983A–01

Addresses (SA), data inputs (DQ), write enable (SW), and chip enable (SE0

and SE1) are all controlled through positive–edge–triggered noninverting reg-

isters. Data enable (DE) is sampled on the rising clock edge while output enable

(G) and match output enable (MG) are asynchronous.

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, pipelined SRAM output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

Compare cycles begin as read cycles with output disabled, so compare data

can be loaded into the input register. The comparator compares the read data

with the registered input data, and a match signal is generated. The match output

is also stored by an output register and released to the match output buffer at the

next rising edge of clock (K).

The MCM69T618 operates from a single 3.3 V power supply and all inputs and

outputs are LVTTL compatible.

•

MCM69T618–5 = 5 ns Clock–to–Match / 10 ns cycle

Single 3.3 V + 10%, – 5% Power Supply

Pipelined Data Comparator

Pipelined Chip Enable and Write Enable for Data (DQ) Output Enable Path

64K x 18 Organization Supports Up to 2MB Cache

Synchronous Data Input Register Load Enable (DE)

Internally Self–Timed Write Cycle

Asynchronous Data I/O Output Enable (G)

Asynchronous Match Output Enable (MG)

100–Pin TQFP Package

REV 5

12/23/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69T618

12 3 4 5 6 7...10

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与MCM69T618TQ5R相关器件

型号	品牌	获取价格	描述	数据表
MCM69T618TQ6R	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, PQFP100, TQFP-100
MCM69T618TQ7R	MOTOROLA	获取价格	Cache Tag SRAM, 64KX18, BICMOS, PQFP100, TQFP-100
MCM69T618ZP5	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69T618ZP5R	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69T618ZP6	MOTOROLA	获取价格	Cache Tag SRAM, 64KX18, 6ns, BICMOS, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69T618ZP6R	MOTOROLA	获取价格	64KX18 CACHE TAG SRAM, PBGA119, 7 X 17 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM6L4400BN50	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 50ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN50R2	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 50ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN60	MOTOROLA	获取价格	1MX4 FAST PAGE DRAM, 60ns, PDSO20, 0.300 INCH, SOJ-26/20
MCM6L4400BN60R2	MOTOROLA	获取价格	Fast Page DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, SOJ-26/20

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