Datasheet > MCM69P737ZP3.2R

MCM69P737ZP3.2R

更新时间： 2024-11-12 10:21:55

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器
页数	文件大小	规格书
20页	282K
描述
Cache SRAM, 128KX36, 3.2ns, CMOS, PBGA119, PLASTIC, BGA-119

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MCM69P737ZP3.2R 数据手册

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SEMICONDUCTOR TECHNICAL DATA

MCM69P737

128K x 36 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

TheMCM69P737isa4M–bitsynchronousfaststaticRAMdesignedtoprovide

a burstable, high performance, secondary cache for the PowerPC and other

high performance microprocessors. It is organized as 128K words of 36 bits

each. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K).

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69P737 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

TQ PACKAGE

TQFP

CASE 983A–01

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

The MCM69P737 operates from a 3.3 V core power supply and all outputs

operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

•

MCM69P737–3.0: 3 ns Access/5 ns Cycle (200 MHz)

MCM69P737–3.2: 3.2 ns Access/5.5 ns Cycle (183 MHz)

MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)

MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)

MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)

3.3 V ± 5% Core Power Supply for MCM69P737–3.0 and

MCM69P737–3.2

•

3.3 V + 10%, – 5% Core Power Supply for MCM69P737–3.5,

MCM69P737–3.8, and MCM69P737–4

•

2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 8

12/10/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69P737

12 3 4 5 6 7...20

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与MCM69P737ZP3.2R相关器件

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MCM69P737ZP3.5	MOTOROLA	获取价格	128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
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