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MCM69P737TQ3.5R PDF预览

MCM69P737TQ3.5R

更新时间: 2024-02-10 01:54:57
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
20页 283K
描述
128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

MCM69P737TQ3.5R 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:LQFP, QFP100,.63X.87
针数:100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.47最长访问时间:3.5 ns
其他特性:PIPELINED ARCHITECTUREI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100长度:20 mm
内存密度:4718592 bit内存集成电路类型:CACHE SRAM
内存宽度:36功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
电源:2.5/3.3,3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.045 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.425 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mm

MCM69P737TQ3.5R 数据手册

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Order this document  
by MCM69P737/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69P737  
128K x 36 Bit Pipelined  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69P737 is a 4M bit synchronous fast static RAM designed to provide  
a burstable, high performance, secondary cache for the PowerPC and other  
high performance microprocessors. It is organized as 128K words of 36 bits  
each. This device integrates input registers, an output register, a 2–bit address  
counter, and high speed SRAM onto a single monolithic circuit for reduced parts  
count in cache data RAM applications. Synchronous design allows precise cycle  
control with the use of an external clock (K).  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable(G) and linear burst order (LBO) are clock (K) controlled through positive–  
edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM69P737 (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls  
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte  
writes SBx are asserted with SW. All bytes are written if either SGW is asserted  
or if all SBx and SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM69P737 operates from a 3.3 V core power supply and all outputs  
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-  
dard JESD8–5 compatible.  
MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)  
MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)  
MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)  
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
PB1 Version 2.0 Compatible  
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
REV 6  
1/20/98  
Motorola, Inc. 1998  

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