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MCM67D709

更新时间： 2024-09-17 22:54:51
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摩托罗拉 - MOTOROLA /
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12页 179K
描述
128K x 9 Bit Synchronous Dual I/O Fast Static RAM

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MCM67D709 数据手册

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Order this document  
by MCM67D709/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM67D709  
128K x 9 Bit Synchronous  
Dual I/O Fast Static RAM  
The MCM67D709 is a 1,179,648 bit synchronous static random access  
memory organized as 131,072 words of 9 bits, fabricated using Motorola’s  
high–performance silicon–gate BiCMOS technology. The device integrates a  
128K x 9 SRAM core with advanced peripheral circuitry consisting of address  
registers, two sets of input data registers and two sets of output latches. This  
device has increased output drive capability supported by multiple power pins.  
Asynchronous inputs include the processor output enable (POE) and the  
system output enable (SOE).  
FN PACKAGE  
PLASTIC  
CASE 778–02  
The address inputs (A0 – A16) are synchronous and are registered on the  
falling edge of clock (K). Write enable (W), processor input enable (PIE) and  
system input enable (SIE) are registered on the rising edge of clock (K). Writes  
to the RAM are self–timed.  
PIN ASSIGNMENTS  
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP  
haveinputdataregisterstriggeredbytherisingedgeoftheclock. Thesepinsalso  
have three–state output latches which are transparent during the high  
level of the clock and latched during the low level of the clock.  
7
6
5
4
3
2
1 52 51 50 49 48 47  
46  
A16  
A15  
PDQ7  
8
9
10  
11  
PDQP  
SDQP  
45  
44  
43  
V
SS  
This device has a special feature which allows data to be passed through the  
RAM between the system and processor ports in either direction. This streaming  
is accomplished by latching in data from one port and asynchronously output  
enabling the other port. It is also possible to write to the RAM while streaming.  
The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.  
Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either  
inputs (D) or outputs (Q) depending on the state of the control pins. In order to  
dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs  
(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.  
PIE will need to track W for proper write/read operations.  
SDQ7  
PDQ6  
SDQ6  
V
12  
13  
42  
41  
SS  
V
PDQ5  
CC  
14  
15  
16  
17  
18  
40  
39  
38  
37  
36  
PDQ4  
SDQ4  
PDQ2  
SDQ2  
SDQ5  
V
CC  
PDQ3  
SDQ3  
V
V
SS  
SS  
PDQ1  
SDQ1  
19  
20  
35  
34  
PDQ0  
SDQ0  
21 22 23 24 25 26 27 28 29 30 31 32 33  
This device is ideally suited for pipelined systems and systems with multiple  
data buses and multi–processing systems, where a local processor has a bus  
isolated from a common system bus.  
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply  
88110/88410 Compatibility: –16/60 MHz, –20/50 MHz  
Self–Timed Write Cycles  
Clock Controlled Output Latches  
Address and Data Input Registers  
Common Data Inputs and Data Outputs  
Dual I/O for Separate Processor and Memory Buses  
Separate Output Enable Controlled Three–State Outputs  
3.3 V I/O Compatible  
High Board Density 52 Lead PLCC Package  
Can be used as Separate I/O x9 SRAM  
PIN NAMES  
A0 – A16 . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input  
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
PIE . . . . . . . . . . . . . Processor Input Enable  
SIE . . . . . . . . . . . . . . . System Input Enable  
POE . . . . . . . . . . Processor Output Enable  
SOE . . . . . . . . . . . . . System Output Enable  
PDQ0 – PDQ7 . . . . . . . Processor Data I/O  
PDQP . . . . . . . . . . . Processor Data Parity  
SDQ0 – SDQ7 . . . . . . . . . System Data I/O  
SDQP . . . . . . . . . . . . . System Data Parity  
V
CC  
V
SS  
. . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
NC . . . . . . . . . . . . . . . . . . . . No Connection  
All power supply and ground pins must be  
connected for proper operation of the  
device.  
REV2  
5/95  
Motorola, Inc. 1994  
1234567...12

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