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MCM6706RJ6 PDF预览

MCM6706RJ6

更新时间: 2024-11-17 21:22:15
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 257K
描述
IC,SRAM,32KX8,BICMOS-TTL,SOJ,32PIN,PLASTIC

MCM6706RJ6 技术参数

生命周期:Transferred包装说明:SOJ, SOJ32,.34
Reach Compliance Code:unknown风险等级:5.8
最长访问时间:6 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:5 V认证状态:Not Qualified
子类别:SRAMs最大压摆率:0.205 mA
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MCM6706RJ6 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM6706R/D  
MCM6706R  
32K x 8 Bit Static Random Access  
Memory  
The MCM6706R is a 262,144 bit static random access memory organized as  
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS  
technology. Static design eliminates the need for external clocks or timing  
strobes.  
J PACKAGE  
300 MIL SOJ  
CASE 857–02  
Output enable (G) is a special control feature that provides increased system  
flexibility and eliminates bus contention problems.  
The MCM6706R meets JEDEC standards and is available in a revolutionary  
pinout 300 mil, 32–lead surface–mount SOJ package.  
PIN ASSIGNMENT  
A0  
A1  
A2  
A3  
NC  
1
32  
31  
30  
29  
28  
27  
Single 5.0 V ± 10% Power Supply  
Fully Static — No Clock or Timing Strobes Necessary  
All Inputs and Outputs Are TTL Compatible  
Three State Outputs  
Fast Access Times: MCM6706R–6 = 6 ns  
MCM6706R–7 = 7 ns  
A14  
A13  
A12  
G
2
3
4
E
DQ0  
DQ1  
5
MCM6706R–8 = 8 ns  
Center Power and I/O Pins for Reduced Noise  
DQ7  
DQ6  
6
7
26  
25  
24  
23  
22  
21  
20  
V
V
8
CC  
SS  
V
V
BLOCK DIAGRAM  
9
SS  
CC  
DQ2  
DQ3  
W
DQ5  
DQ4  
A11  
10  
11  
12  
13  
14  
15  
16  
A
A
A
V
V
CC  
SS  
A4  
A10  
A9  
A
MEMORY  
A5  
A6  
A7  
19  
18  
17  
ROW  
DECODER  
MATRIX  
512 ROWS x 64 x 8  
COLUMNS  
A
A
A
A
A
A8  
NC  
PIN NAMES  
DQ0  
A0 – A14 . . . . . . . . . . . . . . . . . . Address  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
DQ0 – DQ7 . . . . . . . . Data Input/Output  
COLUMN I/O  
INPUT  
DATA  
CONTROL  
COLUMN DECODER  
DQ7  
E
V
V
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
CC  
SS  
A
A
A
A
A
A
NC . . . . . . . . . . . . . . . . . No Connection  
W
G
REV 1  
5/95  
Motorola, Inc. 1995  
For More Information On This Product,  
Go to: www.freescale.com  

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